氬離子植入及百萬電子伏特之質子照射在超大型積體電路上的應用

Abstract

在此論文中首先探討使用氬離子植入於複晶矽或異型矽閘極以防止p型金氧半場效電晶體之硼離子穿透效應。這是因為氬離子植入於複晶膜之上表層中會產生像汽泡的缺陷，抓住了氟離子並因而抑制硼離子的穿透。實驗結果顯示使用氬離子植入於複晶矽或異型矽閘極金氧半元件比傳統元件擁有較小之起始電壓偏移、較佳之介面狀態(Dit)、崩潰電場(Ebd)、崩潰電荷(Qbd)。當應用在p型金氧半場效電晶體時，較佳之電晶體特性可以達到，如次起始振翼(subthreshold swing)、熱載子免疫性 (hot carrier immunity)。 其次，我們也將氬離子植入於氟化硼摻雜之p+/n複晶射極二極體中以抑制複晶矽或異型矽與矽晶體間之介面的磊晶排列。這是由於氬離子植入於複晶矽或異型矽區域所產生似汽泡的缺陷補抓了氟原子因而減少了複晶矽或異型矽與矽晶體間的介面氟原子堆積，如此將導致介面天然氧化物破裂及磊晶排列變的較不嚴重並使接面深度變的較淺。 同樣情形，由於氬離子產生之缺陷也能補抓砷或磷原子，因此我們也將氬離子植入於砷或磷原子摻雜之n+/p複晶射極二極體中以抑制複晶矽或異型矽與矽晶體間之介面的磊晶排列。 另外，我們探討使用百萬電子伏特(MeV)之高能質子照射在矽晶片上以形成半絕緣體的技術，我們找出不同底材濃度與質子照射劑量對最終阻值的關聯性。為了使這項技術可應用於積體電路上，我們開發了兩種方式來克服主動元件與在半絕緣體上形成的被動元件間整合的問題。其一是直接照設在矽晶片上，另外一種是使用鋁罩;前者是使用低劑量之質子照設在原本就較高阻值之晶片上，如此，不但可獲得合乎所求之更高阻值晶片，而且在此低劑量之質子照設下，同時被照射之主動元件只遭受非常輕微之損害且仍可使用，則不需鋁罩之低成本技術在射頻積體電路之應用顯然可行;後者則是直接使用鋁罩以保護主動元件於形成局部半絕緣體時免受照射損害，結果顯示鋁罩可阻擋15MeV，1×1017cm-2之高劑量質子照射。 另一方面，由於半絕緣體形成後仍必須接受塑化包裝以成最終產品，而塑化溫度大約是200℃，半絕緣體之矽晶片經歷此溫度後是否仍舊具備足夠之高阻值必須進一步探討，實驗結果顯示使用鋁罩且經200℃之回火，高能質子照射在矽晶片上仍可維持一定之高阻值以供實際使用。 我們使用被動元件-電感來驗證上述之可行性，實驗結果顯示上述之兩種技術即使在模擬包裝的熱效應下，均可改善電感之品質因子(quality factor) ，因而使擁有高品質因子之被動元件很容易整合在射頻積體電路中。

In this thesis, firstly, a technique to use Ar ion-implantation on the p+ □-Si or poly-Si gate to suppress the boron penetration in p+ pMOSFET is proposed and demonstrated. It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p+ gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (Ebd), interface state density (Dit), and charge-to-breakdown (Qbd) on the gate oxide is obtained. This technique has been applied to fabricate pMOSFET and the fabricated devices exhibit significant improvement on their subthreshold swing and hot carrier immunity. Secondly, this same technique has also been applied to the BF2-implanted poly-Si/Si orα-Si /Si p+/n junction diode to retard the epitaxial realignment. It is due to gettering of F by the bubble-like defects created by Ar implantation in the poly-Si or α-Si region to reduce the pile-up of F at the poly-Si/Si orα-Si/Si interface. This results in less interface native oxide break-up and epitaxial realignment and a shallower junction profile. For the poly-Si/Si diode, it can sustain the rapid thermal annealing at 1050 ℃ for 20 sec; and for the α-Si diode, it can obtain a shallower junction for the rapid thermal annealing to 1075 ℃ and can retard the epitaxial realignment up to 1150 ℃. For the As or P doped n+-p poly-emitter diode during BF2 implantation, the As, P, and F atoms can also be gettered by bubble-like defects created by Ar implantation to reduce their pile-ups at the poly-Si/Si interface, consequently, to cause less break-up of the interface oxide, thus reducing epitaxial realignment. In addition, this thesis also studies issues related with using high energy protons to create local semi-insulating silicon regions on IC wafers for device isolation and realization of high-Q IC inductors. Topics on two approaches, i.e., one using proton direct-write on wafers and the other using Al as the radiation mask were studied. For the unmasking direct write of the proton bombardment, isolation in the silicon wafer can be achieved without damaging active devices if the proton fluence is kept below 1×1014 cm-2 with the substrate resistivity level chosen at 140 ohm-cm, or kept at 1×1015 cm-2 with the substrate resistivity level chosen at 15 ohm-cm. Under the above approaches, the 1hr-200 ℃ thermal treatment, which is necessary for device final packaging, still gives enough high resistivity for the simi-insulating regions while recovers somewhat the active device characteristics. For the masking study, it was shown that Al can effectively mask the proton bombardment of 15 MeV up to the fluence of 1017 cm-2. For the integrated passive inductor fabricated on the surface of the silicon wafer, the proton radiation improves its Q value. Abstract (in Chinese) Abstract (in English) Acknowledgment Contents Figure captions Chapter 1 Introduction 1.1 Motivation 1.2 Thesis outline Chapter 2 Argon Ion-implantation on Polysilicon or Amorphous-Silicon for Boron Penetration Suppression in P+ pMOSFET 2.1 Introduction 2.2 Experiment 2.3 Results and discussions 2.4 Summary Chapter 3 Retardation of Epitaxial Realignment by Implantation of Argon in p+/n Poly-Si or α-Si Emitter Diode 3.1 Introduction 3.2 Experiment 3.3 Results and discussions 3.4 Summary Chapter 4 Gettering of P and As by Ar Implantation on Reducing Epitaxial Realignment in n+/p poly-Si Emitter Diode 4.1 Introduction 4.2 Experiment 4.3 Results and discussions 4.4 Summary Chapter 5 Isolation on Si Wafer by MeV Proton Bombardment for RF Integrated Circuits 5.1 Introduction 5.2 Experiment 5.3 Results and discussions 5.4 Summary Chapter 6 The Effectiveness of Aluminum Mask for Patterning Semi-Insulating Region on Si Wafer under Mev Proton Bombardment 6.1 Introduction 6.2 Experiment 6.3 Results and discussions 6.4 Summary Chapter 7 Conclusion and Recommendation for Further Research 7-1. Conclusion 7-2. Recommendation for further research References VITA Publication List