應用於電路模擬器含有溫度效應的複晶矽薄膜電晶體模式

Abstract

複晶矽薄膜電晶體在大面積主動陣列液晶顯示器的應用潛力上已經受到廣泛的注意。最近，部分應用在電路上的複晶矽薄膜電晶體模式的論文已經被發表，但是卻少有論文將溫度效應考慮在電路模式中。尤其，更無有關具有溫度效應的複晶矽薄膜電晶體模式建立到商用的電路模擬器中。 在本論文中，我們將描述一個具有直流及交流模式的N通道及P通道複晶矽薄膜電晶體的半經驗解析模式。這個模式在次臨界到飽和區間都是可微分且連續，因此是一個非常適用於加入SPICE電路模擬器中的解析模式。在此一模式中，它包含了閘極偏壓誘使晶粒邊界位能降低（GIPBL）、汲極偏壓誘使晶粒邊界位能降低（DIPBL）、通道長度調變、速度飽和效應、Kink 效應及其溫度相依效應。我們的半經驗解析方法是來自於具有物理意義的解析模式。在這個模式中我們用到很少的參數且部分參數都是和元件結構及製成參數相關。除了列出汲極電流模式外，我們亦發展出與直流模式一致的本質電容電壓模式。本質電容電壓模式是從汲極電流模式中推導而來，並考量電荷守恆且克服傳統MOS的電容電壓所遇到的區間不連續的問題。此電容電壓模式中我們一併考慮通道長度調變效應及kink效應對元件特性的影響。在模式值及量測值的比較上，我們可以驗證模式值在廣泛的電壓操作區間且溫度在20oC到200oC中的準確性。在電路模擬的直流分析方面，從量測值及模式值的比較上，我們可以驗證模式的準確性。在電路模擬的交流分析方面，我們串接四級的反相器來預測大面積的元件具有相當嚴重的時間延遲效應。

Poly-silicon thin-film transistors have received extensive attention for their potential applications in the large-size active-matrix liquid crystal display (AMLCD). Recently, quite a few circuit models for poly-silicon TFT have been reported, but very fewer of them took the temperature factors of poly-silicon TFT model into consideration. So far, none have been implemented into commercially available circuit simulator with temperature dependent features. In this thesis, a semi-empirical analytical model for the DC and AC characteristics of both n- and p-channel poly-silicon thin-film transistors is described. It is well-suited for implementation in a SPICE circuit simulator because it is differentiable and continuous from subthreshold to saturation regions. The model includes the Gate Induced Grain boundary Potential Barrier Lowering (GIPBL), Drain Induced grain boundary Potential Barrier Lowering (DIPBL), Channel Length Modulation (CLM), velocity saturation, kink effect, as well as their temperature dependence. Our semi-empirical approach results in a physically based model with a minimum of parameters which are related to the device structure and fabrication process. In addition to the drain current model, the intrinsic Capacitance-Voltage (CV) model is derived. The intrinsic CV model derived from our IV model preserves charge conservation and overcomes the discontinuous problem of conventional MOS CV model. The important effects of kink and channel length modulation are also taken into consideration. Comparisons between the model and measured results show excellent agreement over wide ranges of operating voltages with temperature ranges from 20oC to 200oC. The circuit simulation results of typical poly-silicon TFT circuits in the temperature range from 20℃ to 200℃ are demonstrated. For DC analysis, good agreement between model and measurement can be achieved. For AC analysis, the results of a 4-stage inverter show that timing delay will be serious even for long channel length TFT's. Chapter 2 The Drain Current Model 2.1 Grain Boundary Potential Barrier Height Model 2.2 Drain Current Model in the Strong Inversion 2.2.1 Effective Mobility Model 2.2.2 Linear Region 2.2.3 Saturation Region 2.3 Weak Region and Continuity Chapter 3 The Intrinsic Capacitance Voltage Model 3.1 Intrinsic Capacitance Model in the Strong Inversion 3.2 Comparison with Meyer CV Model Chapter 4 Temperature Deoendence Model 4.1 Parameter Extraction and Optimization 4.1.1 Parameter Extraction Procedure 4.1.2 Parameter Optimization 4.2 Termperature Dependence of Device Parameters 4.3 IV Characteristics of n- and p-channel TFT Chapter 5 Circuit Simulation Results 5.1 Basic Transfer Curve Simulation 5.2 Inverter Circuit Simulation Chapter 6 Conclusions References