以基極偏壓增強熱電子注入操作的快閃式記憶元件可靠性研究

Abstract

近年來，快閃式記憶體已被廣泛地應用於數位相機與手提電腦等可攜式電子產品的資料儲存上。在過去的快閃式記憶體產品的元件多採用n通道元件並使用通道熱電子寫入的方式操作。然而，由於通道熱載子寫入操作需要高電壓以及大量的功率消耗使得其在大量記憶單元寫入操作時顯得困難，在可攜式的應用上，這個問題更加嚴重。最近的研究指出，元件的閘極電流在基板加上一個負偏壓後有大幅度的提升，而在這種操作方式下，汲極電流將被減小，於是以通道熱載子寫入造成大功率散逸的問題可以得到改善。然而以這種方式操作所造成的可靠性問題卻尚未被深入研究過。 在本論文中，吾人針對操作時基極偏壓所得到的效能改善作一比較，接著將快閃式記憶元件中基極偏壓所造成的可靠度問題作一分析，實驗結果指出以基極偏壓方式操作將加速元件的退化。我們發現當元件以基極偏壓方式操作時，所產生的氧化層電荷 (Qox) 將大幅增加，在此也觀察出以基極偏壓增強電子注入所產生的閘極電流在元件退化後會有增大的現象，對於快閃式記憶元件在這種方式操作所造成的容忍度與擾動等可靠性題也做一比較分析。最後我們提出一簡單的方式，在不影響效能的情況下，使用基極偏壓操作的快閃式記憶體所造成的可靠性問題得以改善。

The flash memory has been widely used for application to the digital cameras and hand-held computers as a portable mass storage. In the past, n-channel flash cells with channel hot electron programming were widely used in the design of flash memory products. However, the requirement of high voltage and large power consumption operation in channel-hot-electron programming makes it difficult to maintain a reasonable programming throughput in large memories. This is a critical issue for program intensive portable applications, where power consumption is of major concern. Recently, it was reported that gate current will be enhanced dramatically with the application of substrate bias while drain current can be reduced in such operating conditions. This method may overcome the problem of high power dissipation in channel-hot-electron programming operation. However, the reliability issues related to the substrate bias enhanced hot electron injection scheme have not been reported in the literature. In this thesis, the performance improvement with substrate bias enhanced hot electron scheme is demonstrated and a comprehensive study of the substrate bias induced reliability problems in stacked-gate flash memories are presented. Results show that the applied substrate bias will accelerate device degradation. With substrate bias, we first observed oxide trapped charge Qox greatly increases greatly after substrate biased hot-carrier stress. In addition, we also observed that the gate current induced from substrate enhanced hot electron injection scheme increases after the stress, which has not been reported in the literature. The reliability issues of flash memories including endurance and disturbances were also studied. Finally, a simple method is proposed to suppress the reliability problems during programming without seriously sacrificing the cell performance. Chinese Abstract i English Abstract iii Acknowledgements v Contents vi Figure Captions viii List of Symbols xi Chapter 1 Introduction 1 1.1 The Motivation of This Work 1 1.2 Organization of This Thesis 1 Chapter 2 Device Fabrication and Experimental Measurement 3 2.1 Device Fabrication 3 2.2 Experiments and Measurement Setup 5 2.2.1 Experimental Setup 5 2.2.2 Threshold Voltage Determination 8 2.2.3 Charge Pumping Measurement 10 2.3 Basic Operation Modes of Flash Memories 10 2.3.1 Basic I-V Characteristics of Flash Memories 14 2.3.2 Channel Hot Electron Injection (CHEI) Program 14 2.3.3 Fowler-Nordheim Tunneling Erase 14 Chapter 3 Performance Characteristics of Substrate Enhanced Hot Electron Injection 19 3.1 Principles of Substrate Enhanced Hot Electron Injection, SEHEI 19 3.2 Experimental Results 21 3.2.1 Basic I-V Characteristics 21 3.2.2 Programming Characteristics 21 Chapter 4 Effects of Substrate Bias on Device Degradation 27 4.1 Introduction 27 4.2 Substrate Bias Effect on Oxide Damage 27 4.2.1 Determination of Operation Conditions 27 4.2.2 Experimental Results 29 4.3 Substrate Bias Effect on Gate Current Degradation 36 4.3.1 Experimental Results 36 4.3.2 Discussions 41 4.4 Summary 46 Chapter 5 Substrate Bias Induced Reliability Issues in Flash Memories 47 5.1 Program/Erase Cycling Endurance 47 5.2 Disturbance Characteristics 49 5.2.1 Gate Disturb 49 5.2.2 Drain Disturb 52 5.3 Reliability Improvement by Ramped Voltage Programming 52 5.4 Summary 56 Chapter 6 Summary and Conclusion 60 References 61