使用完全鉬矽化之雙功函數金屬閘極技術

Abstract

我們在金屬氧化物半導體元件閘極結構上提出了一個新的概念圖 ，在N型元件與P型元件的閘極材料分別用鉬的矽化物與純鉬來製作， 這將可以避免掉硼離子的穿隧效應以及獲得良好的熱穩定性。 我們研究使用鉬金屬矽化物薄膜做為金屬氧化物半導體電晶體的 閘極材料及其功函數調變效應，並且探討其平帶電壓與等效介電層厚 度對溫度的熱穩定性。吾人在純氬氣體下，濺渡一層鉬金屬及非晶矽 薄膜，吾人以金屬/二氧化矽/矽基板的電容結構在純氮氣環境下做不 同溫度的快速熱退火處理。並且以同樣製程條件，將鉬金屬與非晶矽 濺鍍於由有機金屬化學氣相沉積法所生長的二氧化鉿介電層薄膜上， 並探討其在高介電值介電層薄膜上形成的鉬金屬矽化物的基本功函數 調變效應以及閘極借電層的熱穩定性。 在功函數調變方面，將鉬金屬矽化物沉積於二氧化矽介電層的閘 極功函數由剛沉積的4.78電子伏特經由快速熱退火處理加溫到攝氏800℃ ，其功函數可調變至4.39電子伏特。而在高介電值二氧化鉿薄膜上所 沉積的鉬金屬矽化物，將使得功函數由4.81電子伏特調變至4.34電子 伏特。在這裡並沒有看到費米能階釘鎖現象，這可能是由於費米釘鎖 能階很接近4.34電子伏特的原因。接著將砷原子使用離子佈值法加入 至鉬金屬矽化物閘極內，進而使以二氧化矽為介電層的金氧半結構其 功函數調降至4.001電子伏特。並且使以二氧化鉿為介電層的元件之功 函數調降至4.16電子伏特。 在熱穩定性方面，藉由快速熱退火處理，將鉬金屬與非晶矽的金 氧半結構電容分別加熱從600℃到950℃ 30秒，探討其平帶電壓與等效 氧化層厚度對溫度的變化，發覺無論是以二氧化矽或是高介電常數二 氧化鉿為介電層的金氧半電容在加熱至攝氏800℃與950℃之間，其平 帶電壓與等效氧化層厚度的變化並不是很大，因此建議以鉬金屬矽化 物作為金氧半結構的金屬閘極其熱穩定性處於可接受範圍。 純鉬在二氧化矽與二氧化鉿上的功函數分別是大約4.93與4.906電 子伏特，非常接近於矽的價帶能階，且功函數與等效氧化層厚度隨著 溫度的變異並不大，可用來製作p型半導體元件。 基於以上的結果，鉬的矽化物與純鉬將可應用於互補式金屬氧化 物半導體元件的製作。

We propose a new schematic structure for gate electrode to fabricate the CMOS device. That is using pure Mo and Mo-silicide gate for pMOS and nMOS device, respectively. That can eliminate the boron penetration, and provide excellent thermal stability up to 950 ℃. First, we investigated the work function adjustability of fully Mo-silicide films and the thermal stability of gate dielectric and equivalent oxide thickness of Mo-silicide MOS devices. The molybdenum and amorphous silicon were deposited by sputtering system in Ar ambient. Samples with metal/SiO2/Si-sub MOS structures annealed at different temperature in RTA (rapid thermal anneal) system in N2 ambient were used to analyze the thermal stability of the flat-band voltage and equivalent oxide thickness. Using the same process condition, the molybdenum and amorphous silicon were deposited on HfO2 high-k Dielectric that deposited by MOCVD system. Investigating the work function adjustability and thermal stability of gate dielectric. The work function of the Molybdenum silicide on SiO2 dielectric decreased from 4.78 eV to 4.39 eV as anneal temperature increased to 800℃ 30s. And on the aspect of the molybdenum silicidation on HfO2 high-k dielectric, the work function was decrease from 4.81 eV to 4.34 eV as anneal temperature increase to 800℃ 30s. The work function of the molybdenum silicide has not seen obvious fermi pinning effect. This may be due to fermi pinning level very close to 4.34 eV. After that, using arsenic ion implantation to add arsenic to gate of MOS structure, to cause the work function of the gate on SiO2 dielectric decrease to 4.001 eV. And the work function of the gate on HfO2 high-k dielectric decrease to 4.16 eV. To investigate the thermal stability of gate oxide and equivalent oxide thickness, the samples were annealed by RTA system from 600 ℃ to 950 ℃, and found that no matter what metal silicide on SiO2 or HfO2 dielectric, the deviation of the metal work function and equivalent oxide thickness annealed among 800℃ and 950℃ can be neglect. Suggesting the molybdenum silicide metal gate can replace the traditional n+ poly-Si gate. The work function of pure Mo on SiO2 and HfO2 is about 4.931 eV and 4.906 eV, respectively. That is very close to the valance band of silicon. The deviation of the metal work function and equivalent oxide thickness annealed up to 950 ℃ can be neglect. Based on these results, Mo-silicide gate for nMOS and pure Mo gate for pMOS may chose for CMOS device fabrication.