無需除法器及低記憶體使用率的適應性多符號算術編解碼晶片設計

Abstract

算術編碼法的壓縮技術，已經被廣泛的應用到工業界許多標準規格上，如JPEG2000、JBIG、JBIG2，然而算數編碼法在實作上，卻有其潛在的困難，由於算術編碼法所採用的編碼方式，是採取依符號出現的機率，做一連串子區間的切割，因此有限長度的精確度、運算複雜度及累積次數統計所需花費龐大記憶體...等，都造成算術編碼法在實作上無法容易實現的主要原因。 基於此，本論文將針對適應性多符號算術編碼法，提出有限歷史長度加權模型的機率模型，來解決適應性算術編碼法在實作時，需使用龐大記憶體的缺點，並進一步的將Coding Pass中，計算複雜且費時的除法器避免，以加速編解碼速度的提升，並進而實現在VLSI Chip上。 我們以TSMC 0.35um 1P4M CMOS的製程，實際製作出一顆晶片，經TimeMill的量測，其最大操作速度可到達66.7 MHz，晶片面積為3.86 mm x 3.86 mm，功率損耗為0.58 W。

The arithmetic coding technique has been proposed in many standards, such as JPEG2000, JBIG, JBIG2. The coding process in arithmetic coding is based on the successive subdivided current interval into subinterval according to the probability model of the current symbol. However, there are some difficulties in implementation, such as the finite length precision, hardware complexity and large memory requirement. This thesis proposes a novel adaptive model for arithmetic coding with a finite weighed history buffer. This architecture can significantly reduce the memory requirement in VLSI implementation. Simulation results from various test input sequences (including audio, speech, image, text, etc) reveal that of our proposed adaptive model is very effective. A customized accumulation counter is designed to replace divisions required for normalization in conventional adaptive models. A prototype chip has been built using TSMC 0.35 1P4M CMOS processes with 66.7MHz operation frequency and the size of 3.86 mm x 3.86 mm. 中文摘要……………………………………………………………..….. i 英文摘要………………………………………………………………....ii 誌謝……………………………………………………………………...iii 目錄…………………………………………………………………..….iv 圖目錄….…………………………………………………………….…vii 表目錄……………………………………………………………..….….x 第一章 緒論………………………………………………………………… 1 1.1 研究背景…………………………………………………………….. 1 1.2 研究動機…………………………………………………………….. 2 1.3 論文章節安排……………………………………………………….. 3 第二章 算術編碼…………………………………………………………... 4 2.1 算術編碼法的原理…………………………………………………. 5 2.1.1 算術編碼法在實數軸( Real Number )上實例……………... 7 2.1.2 算術編碼法實作的困難....................................…………….. 10 2.2 二進制算術編碼法的實例.............................................……………. 14 2.3 算術編碼法效能的分析...................................................................... 24 2.3.1 算術編碼法的效能.................................................................. 24 2.3.2 由Entropy定義來看算術編碼法的效能............................... 25 2.3.3 由邊界值來看算術編碼法的效能.......................................... 27 2.4 算術編碼法的發展.............................................................................. 29 第三章 有限歷史長度加權模型的適應性多符號算術編碼法....... 31 3.1 有限歷史長度模型的適應性算術編碼法.......................................... 31 3.1.1 歷史緩衝區的動作.................................................................. 33 3.1.2 有限歷史長度模型的效能分析.............................................. 34 3.2 有限歷史長度加權模型...................................................................... 38 3.2.1 有限歷史長度加權模型原理.................................................. 38 3.2.2 有限歷史長度加權模型壓縮的效能...................................... 43 3.3 有限歷史長度加權模型在硬體設計上的調整.................................. 60 3.3.1 編碼端除法器的節省.............................................................. 60 3.3.2 解碼端除法器的節省.............................................................. 61 3.3.3 初始值的調整.......................................................................... 62 3.3.4 計算時間比較.......................................................................... 63 第四章 硬體架構設計……………..........................................…………… 66 4.1 編解碼的系統架構.............................................................................. 66 4.2 中央控制單元...................................................................................... 67 4.3 機率模型單元...................................................................................... 70 4.3.1 歷史緩衝區電路...................................................................... 70 4.3.2 累積機率統計電路.................................................................. 72 4.4 上下邊界值計算單元.......................................................................... 77 4.5 符號搜尋單元...................................................................................... 81 4.6 正規化單元.......................................................................................... 82 4.7 測試考量.............................................................................................. 87 4.7.1 內部電路的測試考量.............................................................. 87 4.7.2 輸入為特殊vector的情況...................................................... 87 4.7.3 功能的測試.............................................................................. 88 第五章 晶片製作與效能分析……................................................……… 89 5.1 晶片規格.............................................................................................. 89 5.1.1 輸出/入接腳............................................................................ 89 5.1.2 晶片佈局圖及打線圖.............................................................. 92 5.1.3 晶片的特性.............................................................................. 94 5.2 模擬結果與效能分析.......................................................................... 95 5.2.1 晶片模擬結果.......................................................................... 93 5.2.2 軟體與晶片效能的分析.......................................................... 97 5.3 相關算術編解碼晶片的效能分析..................…................................ 99 第六章 結論與未來展望……………………………………………….. 104 6.1 結論………………………………………………………………….. 104 6.2 未來展望…………………………………………………………….. 105 參考文獻………………………………………………………………………… 106