IEEE 802.16a 分時雙工正交分頻多重進接上行傳收系統在數位訊號處理器平台上之整合及最佳化

Abstract

本篇論文主要介紹IEEE 802.16a 分時雙工正交分頻多重進接上行傳輸系統的軟體實現，我們整合前向誤差改正編碼器於傳送端，並於接收端加入同步裝置、通道等化裝置、及前向誤差改正解碼器。 我們先針對接收端的同步演算法做些修改，並在數位訊號處理 (DSP) 平台上對程式做最佳化的處理。我們的數位訊號處理平台包括一台個人電腦、Innovative Integration公司的Quixote板子及其上裝置的Texas Instrument 公司的TMS320C6416 數位訊號處理晶片。 我們在接收端的上行同步處理機制是利用上行傳輸資訊 (preamble) 的不變性，直接對收到的信號作相關性 (correlation) 的運算。藉此找到第一個到達基地台之使用者的時間，以減低符元間的干擾 (inter symbol interference)。 為了能有效提升DSP運算效率，我們系統中所有的運算皆是以定點 (fixed-point) 的格式來處理。而最佳化的目標是加速程式執行的速度，以期能達到即時運算的要求。我們提出數個針對程式所做的改善技巧，如軟體管線 (software pipelining)，或是使用C6416內具有的指令 (intrinsic) 來做處理。並從編譯器所提供的相關資訊做進一步的分析討論，以清楚了解程式的運作情形。 最後，傳送端的插值濾波器 (interpolator filter) 及接收端同步器的速度分別改善了85.85倍和1.74倍，且在DSP上執行的效率也各達到90.94%和85.87%。

This thesis introduces the software implementation of the IEEE 802.16a TDD uplink transceiver system. We integrate the FEC encoder in the transmitter, the synchronizer, the channel equalizer, and the FEC decoder in the receiver. We first do some modifications to the uplink synchronization algorithm, and then optimize our programs on the digital signal processing (DSP) platform, which includes a personal computer (PC), Innovative Integration’s Quixote DSP board, and the TI’s TMS320C6416 DSP chip. The uplink synchronization mechanism is using the invariance of the preamble which is also known to the base station. We correlate it to the received signals directly, and thus find the first coming subscriber station’s time to reduce the inter-symbol interference. The data formats on this system are all “fixed-point” for improving the computational efficiency in DSP. Our optimization goal is to accelerate the program’s execution speed so that it can satisfy the requirement of real-time processing. We present some optimization techniques, such as software pipelining, and using the intrinsics of DSP, to deal with the most time-consuming parts of the program. We also discuss and analyze the compiler feedbacks to understand how the program works in the DSP. Finally, the speed of the interpolator filter in the transmitter and the uplink synchronizer in the receiver can be improved by 85.58 and 1.74 times, respectively. The computational efficiencies of them are 90.94% and 85.87%, respectively.