非同步處理器模擬器之設計與實作

Abstract

這些年來，非同步處理器成為新一代計算機結構的熱門研究方向。為了能在不用真正製造出硬體的情況下，還能比較不同設計方法的優劣，我們需要一個軟體層級的模擬器。我們設計SimAsync-非同步處理器模擬器-來幫助未來在非同步架構的研究。這套工具建基於一套現代處理器的模擬器：SimpleScalar，其中包含了對計算機架構的說明及一些輔助工具。 我們設計並實作出一個非同步處理器的模擬器，在本論文中有對非同步架構的介紹及設計與實作的細節的說明。

Asynchronous processors have become a new direction of modern architecture research these years. To compare the improvement of different approaches without designing a real ASIC, we need a code-based simulator. That's the reason we want to design SimAsync, an asynchronous processor simulator, for researches in asynchronous architectures. The simulator tools are based on SimpleScalar[1], a public simulator of modern microprocessors, and contain a complete description of the target processor architecture, and many details about the internals of the tools. We design and implement an asynchronous processor simulator. In this thesis, we cover the introduction of asynchronous architecture and details of the design and implementation issues.