以連線為導向的平面設計中考量雜訊效應之緩衝器規劃

Abstract

隨著製程技術進步到深次微米時代，連線對電路效能及訊號整合而言已是決定性的要素。更明確地說，當超大型積體電路設計(VLSI)相關技術進步、元件尺寸與間隔縮小、耦合電容與電感效應增加之影響因素下，由干擾(crosstalk)所引起的雜訊更為重要。插入及改變緩衝器尺寸是現有技術中用以降低連線時間延遲與耦合電容效應最有效且最普遍的方法。在傳統超大型積體電路設計上，一般在電路佈局(layout)後才插入或改變緩衝器尺寸；然而，於電路佈局後才插入或改變尺寸的緩衝器數目高達數十萬、甚或百萬時，因大部份繞線區域已被佔據，將使得緩衝器難以插入。因此，將緩衝器之規劃由傳統電路佈局後提前至平面設計階段中以確保在合理時間中能完成可行的設計，即達成時間封閉性及設計收斂性。在此論文中，我們首先推導出插入緩衝器以求時間延遲與降低雜訊最佳化之公式，並進一步應用此公式來計算同時滿足時間延遲與雜訊兩種限制的可行的區域(feasible regions)，亦即求兩種限制的可行的區域的交集。尤其我們推導出理論以證明為何等距離插入緩衝器可達成時間延遲最佳化，此理論公式應用自由度觀點，使先前的研究中所作的假設轉化為此一般化理論公式中自由度等於一的的特殊狀況，因而改進先前的研究中所作的假設中過於簡化又未加以理論證明與解釋之缺失。根據實驗結果，我們的方法不僅多考量雜訊限制，且在效能上所達成之成功率為80.8%，而只須付出額外0.54%面積的代價；相形之下，先前的研究[13] 未考量雜訊限制，且在效能上所達成之成功率為72.8%，而多付出額外1.20%面積的代價。

As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Crosstalk-induced noise has been attracting increasing attention when technology improves, spacing diminishes and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert/size hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this thesis, we first derive formulae of buffer insertion for timing and noise optimization, and then apply the formulae to compute the feasible regions for inserting buffers to meet both timing and noise constraints. Especially, we derive a general formula to release the previous simplified assumption that buffers are inserted in equal distance. By applying degrees of freedom, our theorem proves and explains why and how buffers inserted in equal distance can optimize delay, and this is the special case with the degree of freedom equals one. Experimental results show that our approach achieves an average success rate of 80.8% of nets meeting both timing and noise constraints and consumes an average extra area of only 0.54% over the given floorplan, compared with the average success rate of only 72.8% meeting timing constraints and an extra area of 1.20% by [13].