IEEE 802.16a 分時雙工正交分頻多重進接下行傳收系統之數位訊號處理器軟體實現與整合

Abstract

我們在此論文中介紹IEEE 802.16a 分時雙工正交分頻多重進接之下行傳收系統。 傳收系統包含了在數位訊號處理器上實現發射端、同步裝置、通道狀態估測器和其他接收端功能，以及在電腦主機上實作通道模擬器來模擬多路徑衰減、外加白色高斯雜訊以及頻率偏移等通道效應。下行同步技術包含了符元(symbol)開始時間、頻率偏移和資料訊框(frame)之估測。我們使用德州儀器(TI)所製造的數位訊號處理器。此處理器的操作平台為Innovative Integration 公司製名為Quixote的cPCI卡。

程式主要都是用16位元(bit)的定點(fixed point)格式來完成。我們藉著改變程式編碼的風格(coding style)以及C6416本身具有的指令來改進程式執行的效能，並把執行效能拿來跟能否達到即時運算的要求做比較以及分析。此外，我們還在電腦主機上做了一個用來在螢幕上監控同步裝置以及通道狀態估測器的圖形介面。 我們發現若要整個系統都達到即時運算的要求就需要把各個功能都分割到多顆數位訊號處理器上來實現。

This thesis presents an implementation of IEEE 802.16a TDD OFDMA DL transceiver system, which includes the implementation of transmitter, synchronizer, channel estimator, and other receiver functions on the DSP baseboard and channel simulator, which simulates multipath fading, AWGN and frequency offset, on host PC. The DL synchronization includes the estimations of symbol timing, frequency offset, and frame lock status. The implementation employs Texas Instruments’ TMS320C6416 DSP chip housed on Innovative Integration’s Quixote cPCI card.

The program is mainly implemented by 16-bit fixed point data format. Performances of the programs are analyzed and improved by changing the coding style and applying intrinsic function of C6416 DSP. The execution performances are compared to the real-time requirement. Besides, we also implement a host graphical interface which can monitor the synchronization and channel estimation results on the screen. We find that we may need to separate the functions into multi-DSPs to achieve the real-time of the overall system.