頻率合成器的分析設計與其在同步光學網路之應用

Abstract

本論文提出並分析完全積體化的頻率合成器。藉著使用相同的核心元素， 應用在同步光學網路上的電路亦在此提出。二者分別以0.8微米及0.6微 米的N型井互補式金氧半製程完成電路的設計、模擬與晶片製作。 論文中對電路模擬結果及量測資料均有充份的討論節解釋。 首先, 所提出的頻率合成器是單晶片設計亦即是不需要再外接任何 離散元件。由於採用了對稱式動態負載，此電路便避免遭到來自電 源引進之雜訊影響。此外，因為外加一個電流路徑，使得此頻率合 成器可在極低頻帶工作以達到寬頻帶的頻率輸出能力。使用0.8微米 的金氧半製程，量測結果顯示輸出頻率可達到1至600百萬赫茲•而 且在150百萬赫茲輸出(壓控振盪器工作在300百萬赫茲)時，輸出時間 抖動只有正負80ps，而在3.3伏特工作電壓下，只有18釐瓦的功率損耗。 其次，架構在此頻率合成器的迴路結構下，本論文亦提出並分析了一個 SONET STS-1 解同步器。在文中亦詳述SONET STS-1的背景資料與系統需求。 使用相位跳躍和負回授兩種技術，我們設計了一個全新架構的解同步器。 相位跳躍技術使得電路有著更精確的相位控制並有很低的時間抖動輸出； 而負回授技術則使得電路的FIFO需求大幅減少並降低製作成本。 模擬結果顯示系統輸出達到了1.5UI的規格要求。 最後, 對於再進一步的應用在 SONET STS-3 上的可能行性亦詳加討論。 我們相信可在對電路做極少修改的況況下達到新的需求。

In this thesis, a fully integrated CMOS frequency synthesizer is proposed and analyzed. With the same core cell technique, its application in SONET network is also proposed. They have been successfully designed and fabricated in 0.8$\mu$m and 0.6$\mu$m CMOS N-well SPDM technology, respectively. The simulation results and measurement data are discussed and explained in this thesis. Firstly, the frequency synthesizer are proposed and integrated in a single chip without any external discrete components. It adpopts the symmetric load in the delay cell of ring-oscillator to avoid power-induced noise. Additional current path for low-frequency operation is used to make the frequency synthesizer have the wide-band operating capability. Fabricated in 0.8$\mu$m CMOS process, the measured output frequency range is 1 to 600MHz. The synthesizer has demonstrated peak-to-peak jitter of $\pm$80ps at 150MHz(VCO at 300MHz) with 3.3V supply and 18mW power dissepation. Secondly, based on the synthesizer loop structure, the SONET STS-1 desynchronizer is contructed and analyzed. The background and requirement of SONET STS-1 is described in detail. Applying phase-hopping an d negative-feedback techniques, a new artitecture for SONET network application is present. The phase-hopping technique produces low-jitter output; and the negative-feedback technique reduces the size of FIFOs and cost. Simulation results show that the specification of 1.5UI output jitter is achieved. Finally, the further application in SONET STS-3 is discussed. It is possible to implement by minor modification of the desynchronizer architecture.