标题: 用于低功率系统晶片上时脉与暂存器组设计之研究
The Study on the Clocking Techniques and Register File Design for Low Power SoC
作者: 钟启睿
Chi-Jui Chung
任建葳
Chein-Wei Jen
电子研究所
关键字: 低功率;时脉;多重频率;不同状态;快速傅立叶转换;暂存器组区块化;记忆体分割;Low power;Clock;Multiple Frequency;Distinct phase;FFT;register file banking;memory partitioning
公开日期: 2000
摘要: 时脉(clock)和记忆体向来都是超大型积体电路(VLSI)中两个主要消耗功率的子系统(subsystem)。这个领先的情况随着制程快速进步会越来越明显,因为时脉讯号速度持续的向上攀升、并且越来越多的应用整合大量的记忆体进单晶片上。我们在这篇论文中提出这两个子系统消耗功率的模型并且分别加以探讨。
我们认为依各个区块的运算特性划分为不同的时脉区域(clock domain),并分别供给其需要的时脉讯号可以大幅降低时脉子系统的功率逸散(power dissipation)。我们将这个想法实际应用在一个多率(multirate)的快速傅立叶转换(FFT)架构中。在晶片大小约略相同的情况下,我们降低了时脉子系统约五成(47% ~ 51%)的功率消耗,相当于省下了整个架构上大约两成(14% ~ 28%)功率。
记忆体分割(memory partitioning)是个常用的省电方法,我们运用这个方法在低功率暂存器组(register file)的设计中。暂存器组分割可以有效的降低功率但需付出一些额外的代价(overheads),于是我们在这篇论文中提出了一个简单的模型,不需事先布局(layout)就可以精确预估最佳分割的大小,我们的实验结果和实际的布局后模拟(post-layout simulation)完全吻合。所有的实验数据皆附在各章节末。
The clock and the memory subsystems contribute most of the power dissipation in a SoC design. In this thesis, we examine these two major power consumers and develop the simplified power dissipation model for each of them. First, we propose a low-power clock subsystem with multi-phase clocks at a reduced frequency for our multirate FFT implementation. The proposed clocking scheme reduces 47% to 51% power dissipation on the clock network and saves 14% to 28% overall power with a comparable silicon area. Then, we propose the optimal register file banking to illustrate the power reduction techniques for the memory subsystem. The proposed simple model for power estimation in the banked register file correctly guides the optimization process to find the banking number that consumes the least power. The results are consistent with the HSPICE post-layout simulation. Both the simulation and implementation results are available at the end of each chapter.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT890428029
http://hdl.handle.net/11536/67100
显示于类别:Thesis