晶圓尺寸記憶體整合的設計自動化之研究

Abstract

電腦技術的進步促使了高速、高容量記憶體的需求。現今的生產技術將封裝好的晶片整合在印刷電路板上形成記憶體模組(memory module)，而此篇論文將提出兩種架構及對應的的分區(partitioning)、配置(placement)及繞線(routing)的方法以能在封裝前直接在晶圓層級整合記憶體模組，這個方法將能有效地減少模組面積、增進記憶體效能及提高利潤。首先以能獲取最大利潤為考量將晶圓劃分成適當的模組(feasible module)，並提出一個以多項式成長(polynomial time)的配置方法來最小化模組的最差延遲(critical delay)，最後再決定其繞線並用雷射切割(laser cutting)技術打斷不需要的連線。實驗結果顯示，我們的方法效果相當好且非常有效率。一片具有379個晶片、良率為86.28%的晶圓，僅花費0.02秒的執行時間及976KB的記憶體完成分區工作，且比最原始的分區方法獲得兩倍以上的利潤。另外，一個64MÍ128bits的模組整合工作最多花費348.38秒執行時間及4664KB記憶體完成，而其模組延遲獲得了88.67%的進步。

The progress of computer technology triggers the requirement of high speed and large volume memory. In modern manufacturing, a memory module is integrated by packaged memory chips on a printed circuit board. This thesis proposes two architectures and corresponding partitioning, placement and routing approaches aimed at integrating a memory module at the wafer level before packaging. This method can effectively reduce the area, enhance the performance, and raise the profit for memory modules. The partitioning approaches divide a wafer into feasible modules to earn the highest profit. A polynomial time algorithm is proposed to find the placement that minimizes the critical delay of the module. The routing is subsequently applied, and the laser cutting technology is adopted to remove the unnecessary connections. Experimental results show that our methods are very effective and efficient. A wafer with 379 dies (yield = 86.28%) can be partitioned in 0.02 second runtime and 976KB memory and earns more than twice the profit obtained by the simplest original approach. In addition, a 64M x 128bit module is integrated in 348.38 second runtime and 4664 KB memory, and the delay improvement is achieved 88.67%.