低功率循序串列於繞線端最佳化方法研究

Abstract

隨著深次微米超大型積體電路製造技術的的進步，我們可以將系統整合到單晶片上。 由於系統單晶片的複雜度極高，測試電路在設計上也因而遇到許多挑戰。在所有測試電路的設計技巧上，嵌入式掃描串列(scan-based built-in-seft-test)架構在工業界上最被普遍應用。然而，當掃描串列沒有良好的佈局或順序時，他們在電路測試階段將比正常工作時消耗更多的功率。這些多出來的功率消耗將可能導致晶片製造良率下降及突然的電路損害。在這篇論文，我們將提出一個有效的方法來同時降低測試功率消耗及降低掃描串列所造成的繞線成本。由實驗結果可以得知我們的方法跟之前的利用分割電路方法的論文做比較的話，在相同的繞線成本下，最多可以減少至少百分之十以上的測試功率消耗。

With advanced VLSI manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC design, circuit testability becomes one of the most challenging work. Among design for testability (DFT) techniques, scan-based built-in self-test (BIST) architectures are widely used in industry. However, without careful design in scan cell placement and chain ordering, circuits consume much more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this thesis, we present an effective approach to simultaneously minimizing test power and routing cost in scan chain design after cell placement. The experimental results are encouraging. Compared with a recent result in [6], which uses the approach with clustering overhead, we obtain up to 10% power saving under the same routing cost.