P型通道超薄氧化層金氧半電晶體低電壓下陷阱對陷阱的穿透

Abstract

當金氧半場效電晶體逐漸縮小時，氧化層的的厚度開始進入了直接穿透範圍。但是，漏電流的機制尚未被完全瞭解。本論文討論在低電壓之下基極電流產生機制。我們測量P型通道超薄氧化層金氧半場效電晶體在載子分離架構之下的基極電流。此量測元件是利用0.18微米製程所生產出三種不同厚度。閘極大小是10000和62500 微米平方。我們提出陷阱對陷阱的穿透來解釋實驗量到的資料。載子分離架構之下P型通道超薄氧化層金氧半場效電晶體的低電壓基極電流是起因於電子從氧化層/n型井的介面陷阱穿透到P型多晶矽/氧化層的介面陷阱。 在0伏特至1伏特所淬取出的參數可以被閘極電壓小於-1V的實驗和物理模型資料所證實，其電子是由p型多晶矽/氧化層的介面陷阱穿透到n型井的導帶。在定電流p型多晶矽價帶電子穿透加壓實驗中，我們觀察到低電壓加壓引發漏電流。此現象是起因於介面陷阱的增加。我們利用所建立的物理模型觀察氧化層的退化得到兩個重點：（i）所淬取的介面陷阱密度增加量和加壓注入電荷量有次方的關係。（ii）固定注入電荷下，介面陷阱密度增加量隨著氧化層厚度減少而減少。

The gate oxide thickness in aggressively scaled MOSFETs is now approaching the direct tunneling regime. The mechanism of leakage current isnt completely understood. This thesis discusses the mechanism of substrate current at low voltage(0V <VG< VFB). We measure substrate current in ultrathin gate oxide pMOSFETs in a carrier separation configuration. The p+ poly-gate pMOSFETs were fabricated by a 0.18-um process technology with three different oxide thicknesses. The gate dimensions were drawn to 100x100 um2 and 250x250 um2. We present trap-to-trap tunneling to explain measured data. The low voltage substrate current of ultrathin gate oxide pMOSFETs in a carrier separation configuration is attributed to electron tunneling from oxide/n-well interface state to p+-poly/oxide interface state. The parameters used or extracted in 0V <VG< 1V are confirmed by alternative measurement in VG< -1V. In the range of VG< -1V, electrons tunnel from polysilicon interface state to conduction band of N-substrate. During stress experiment via p+-poly valence band electron tunneling, the low voltage stress induced leakage current (LV-SILC) is observed. We attribute LV-SILC to increasing interface states. The ability of sensitively monitoring tunnel oxide degradation is highlighted: (i) extracted interface state density increment Nit follows a power law with stress injection charge Qinj; and (ii) for given Qinj, Nit dramatically decreases with oxide thickness reduction.