Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 張加易 | en_US |
dc.contributor.author | Chia-Yi Chang | en_US |
dc.contributor.author | 陳宏明 | en_US |
dc.contributor.author | Hung-Ming Chen | en_US |
dc.date.accessioned | 2014-12-12T02:25:34Z | - |
dc.date.available | 2014-12-12T02:25:34Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009211642 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/67201 | - |
dc.description.abstract | 隨著製程的進步,越來越多的電路可以整合進去單一的晶片裡面,這同時也代表在現今的設計裡面需要越來越多的輸出輸入單元。覆晶式設計跟傳統的週遭式焊接線設計相比,它更適合需要大量輸出輸入的設計,在這篇論文裡面我們提出了一個覆晶式設計的輸入輸出緩衝器區塊與核心單元擺置的演算法,他針對面積、接線長度、信號的不對稱做優化,這各演算法可以銜接既有的擺置方法,將原來的擺置做成覆晶式的設計,實驗數據顯示我們的方法跟傳統週遭式焊接線設計有更好的效能,特別是在擁有更多的輸出輸入單元的設計上。 | zh_TW |
dc.language.iso | en_US | en_US |
dc.subject | 擺置 | zh_TW |
dc.subject | 覆晶式 | zh_TW |
dc.subject | 輸入輸出緩衝器 | zh_TW |
dc.subject | placement | en_US |
dc.subject | flip-chip | en_US |
dc.subject | I/O buffer | en_US |
dc.subject | area array I/O | en_US |
dc.title | 以效能為導向之輸入輸出緩衝器區塊與核心單元擺置的覆晶式設計 | zh_TW |
dc.title | Performance Driven I/O Buffer Block Planning with Core Placement in Flip-Chip Design | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
Appears in Collections: | Thesis |
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