小尺寸薄膜電晶體之研究

Abstract

本論文主要是探討小尺寸複晶矽薄膜電晶體元件特性之變化，除了改變不同的通道尺寸外，還配合上改變通道層複晶矽薄膜的厚度和複晶矽晶粒的大小，以觀察通道對薄膜電晶體元件特性的影響。另外，為了觀察通道側壁與通道中缺陷密度對元件特性的影響，我們利用多通道元件來放大這兩個效應，並分別改變通道寬度及通道數目來分析元件特性所受到的影響。 我們以標準製程製作各種不同尺寸的薄膜電晶體及多通道薄膜電晶體。接著我們量測並觀察這些元件的基本電性。最後，根據量測所得的實驗結果，我們試著提出合理的機制來解釋尺寸及結構對元件特性造成的影響。 元件尺寸上的變化主要為下列三種：（1）短通道元件：元件的通道長度由10微米縮小至0.8微米，而通道寬度維持一定；（2）窄通道元件：元件的通道寬度由10微米變化到0.8微米，而通道長度維持一定；（3）多通道元件：改變通道數目為1條、4條和8條通道，觀察通道側壁的影響。以及改變通道寬度由10微米變化到0.8微米來觀察通道中缺陷密度的影響。 最後根據實驗結果,我們發現當通道寬度變窄，元件特性會變好。這主要是因為通道中的缺陷密度變少，我們也利用多通道薄膜電晶體結構印證並分析了這個結論。除此之外，我們另外發現了多通道薄膜電晶體改善基本電性的特質必須建立在通道寬度很小的前提之下，利用改變通道層的厚度、閘極電壓和晶粒尺寸都能增加基本特性改善的幅度。在較大汲極電壓時，隨著通道長度變短，汲極電流會不受閘極電壓控制的大幅增加，臨界電壓的變化也非常的劇烈，這些現象主要是由衝擊游離效應所造成的。但在汲極電壓很小時，我們依然觀察到這些現象，為此我們也提出晶粒邊界的衝擊游離機制來解釋這個現象。

In this thesis, small dimension poly-Si TFTs with different dimensions, poly-Si film thickness, and grain size are fabricated and characterized successfully. In addition, the multichannel devices were chosen to investigate the influence of channel sidewall and trap density on device performance. Finally, the mechanism of dimensional-related electrical behavior was proposed properly to explain our experimental result. Our devices are divided into three groups. (1) Narrow width devices are devices with various channel widths and fixed channel length. (2) Short channel devices are devices with various channel lengths and fixed channel width. (3) Multichannel devices are devices with various number of channel finger and fixed channel width, and devices with various finger widths and fixed number of channel finger. All the devices exhibit typical electrical characteristics, the result shows that device performance is improved as the width decreases. This is resulted from the reduction of trap density. The behaviors of multichannel devices also support this inference. Multichannel devices can improve performance only when their finger widths are quite small. Thinner channel thickness, larger gate voltage, and larger grain size can enhance this improvement. Severe threshold voltage roll-off and obvious kink effect under high drain voltage is due to the impact ionization at drain side. However, in our experiment, serious threshold voltage roll-off was observed even under low drain voltage. The body potential was also raised dramatically in this low drain voltage region. According to poor gate voltage controllability at body side and the narrow depletion regions on poly-Si grain boundaries, we proposed a plausible grain-boundary impact ionization mechanism to explain the result of this experiment.