標題: | 免衰減操作無自迴授比例式記憶細胞 The Design of CMOS Non-Self-Feedback Ratio Memory Cellular Nonlinear Network without Elapsed Operation for Pattern Learning and Recognition |
作者: | 吳諭 Yu Wu 吳重雨 Chung-Yu Wu 電子研究所 |
關鍵字: | 類神經網路;比例式記憶;CNN;Ratio Memory |
公開日期: | 2005 |
摘要: | 在圖形辨識的領域上,聯想式記憶是一個相當熱門的辨識方法,而無自迴授比例式記憶類神經網路則已被證實可以作為一種聯想式記憶的實現方法。然而,無自迴授比例式記憶類神經網路需要一段漏電操作以產生高辨識率的比例鍵值,而這段漏電操作的時間則會因所學習的圖形不同而改變,造成圖形辨識上的困擾。
本論文的主旨在於闡述免漏電操作無自迴授比例式記憶細胞非線性網路架構之分析與設計及其在聯想式記憶及圖像辨識上之應用。免漏電操作無自迴授比例式記憶類神經網路在產生高辨識率的比例鍵值時,無須使用到漏電操作,可在圖形學習完畢後,直接產生所需的比例鍵值,並達到和原本比例式記憶類神經網路相同的辨識率。
本論文中引述了免漏電操作比例式記憶類神經網路所用以直接產生比例鍵值的理論,並實際用TSMC 0.35um 2P4M Mixed-Signal製程設計了一個解析度為9x9的免漏電操作比例式記憶類神經網路,並實現之且加以量測。電路中用到架構簡單的比較器,以節省面積。並使用計數器和比較器的組合以簡單地達到免漏電產生比例鍵值的目的。此設計中,還加上了得以任意輸入所希望學習的圖形的介面,因此,此電路可以學習任何9x9的圖形。另外,本論文中的設計省略了原本無自迴授比例式記憶類神經網路所需要的乘除法器,使得此設計的單位面積比原本的無自迴授比例式記憶細胞非線性網路來的小。
在量測上,雖然所學習的三個圖形,有一個辨識的不順利,但此論文也對造成此結果的原因做了探討。並重新設計電路,在Hspice模擬上驗證新電路確實可以改善此缺陷 The associative memory is a hot topic in domain of pattern recognition. It is proven that the non-self-feedback ratio memory nonlinear network (RMCNN) with elapsed operation can be used as a kind of associative memory. However, the RMCNN with elapsed operation needs a elapsed period to get the feature enhanced ratio weights. The elapsed period changes as learning patterns change, and thus the elapsed operation let the process of pattern recognition inconvenient. This thesis expounds the design and usage of RMCNN without elapsed operation (RMCNN w/o EO) in the domain of pattern recognition. The RMCNN w/o EO doesn’t need the elapsed period when it generates the feature enhance ratio weights. The design in this thesis can generate the feature enhance ratio weights directly after pattern learning, and it has a good recognition rate that is the same with RMCNN with elapsed operation. This thesis quotes the theory used to generate the feature enhance ratio weights directly. In this thesis, the circuit of RMCNN w/o EO is designed and a 9x9 RMCNN w/o EO is implemented by TSMC 0.35um 2P4M mixed-signal process. A simple comparator is used to save chip area. The counters and comparators let the ratio weights without elapsed operation be generated easily. In this design, a pattern input interface that can input any patterns into the circuit is implemented too. Thus this chip can learn any patterns. Besides, the design in this thesis didn’t use the M/D in the RMCNN with elapsed operation, and the area of one cell is smaller than the RMCNN with elapsed operation. The experimental result isn’t successful completely. One of the three learning patterns isn’t recognized successfully. This thesis discovers the cause of the experiment defect, and the circuit is redesigned. The new circuit operates well in the simulation result. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009211657 http://hdl.handle.net/11536/67368 |
顯示於類別: | 畢業論文 |