低密度對偶檢查碼結構之改進以及其解碼器之超大型積體電路實現

Abstract

由於低密度對偶檢查碼 (LDPC) 的編碼增益接近向農 (Shannon) 極限以及解碼程序上擁有低複雜度的特性，所以在近年來受到廣泛的討論。本文中，我們利用差分集合 (difference family) 的概念來建構一種新的低密度對偶檢查碼結構，此結構在編碼上擁有低複雜度的特性，以及在解碼器的設計上易於超大型積體電路 (VLSI) 實現。此外，在解碼器的設計上，我們使用部分平行 (semi-parallel) 的架構並使其平行度為10，設計一個碼率為3/4、長度為960位元、最大循環解碼次數為10的非規則低密度對偶檢查碼解碼器，在0.18 製程下，此解碼器之資料流為每秒370MHz、面積為80萬個邏輯閘、消耗功率為550mW。

In recent years, low-density parity-check (LDPC) codes have attracted a lot of attention due to the near Shannon limit coding gain when iteratively decoded. In this thesis, we construct a new structure of irregular LDPC codes based on using the difference families. The resulting codes can be encoded with low complexity and are suitable for the VLSI implementation of their decoder. With the semi-parallel architecture and a parallel factor of 10, an irregular LDPC decoder has been implemented, of which the code rate is 3/4, the code length is 960 bits, and the maximum number of decoding iterations is 10, respectively. The irregular LDPC decoder can achieve a data decoding throughput of up to 370Mbps, an area of 800k gate counts, and a power consumption of 550mW using the UMC 0.18 ASIC process technology.