適用於Serial-ATA之展頻時脈產生器

Abstract

隨著對高速傳輸速率需求的不斷提升， Serial AT Attachment (Serial-ATA)成為一種普遍的外部儲存規格。隨著電路運作速度的增快，高速時脈信號所造成的電磁干擾(Electro-Magnetic Interference, EMI)成為不可忽視的問題。因此 Serial-ATA系統要求時脈頻率具有5000 ppm展頻量、30~33 kHz調變率。 在本論文中，我們提出一個適用於Serial-ATA之展頻時脈產生器(Spread Spectrum Clock Generator, SSCG)。展頻技術是利用對時脈信號頻率做調變以有效降低電磁干擾。我們使用一個具備三階三角積分器的除小數鎖相迴路來實現展頻時脈產生器。除小數鎖相迴路可合成出比參考頻率小的頻率，使用數位式三角積分調變技術可將量化雜訊調變到高頻以減少spur現象。 論文中我們實現了一個1.5 GHz，具有5000 ppm、33 KHz三角波調變的展頻時脈產生器。此展頻時脈產生器使用台積電0.18 um CMOS製程製造。在非展頻情況所量測到時脈jitter為80 ps。展頻模式下，頻譜上的時脈峰高能量降低了23.44 dB。

As the increasing demand for high data transmitting rate, Serial AT Attachment (Serial-ATA) is one of the popular external storage specifications. As operating at high frequencies, currents and voltages present in the circuits and the signal traces lead to great Electro-Magnetic Interference (EMI). Hence, Serial-ATA systems require a wide spreading of 5000 ppm and a 30~33 kHz modulation rate. In this thesis, we proposed a Spread Spectrum Clock Generator (SSCG) for Serial-ATA. SSCG is a special technique of frequency modulation to reduce EMI effectively. We use a fractional-N PLL with a digital 3rd order MASH 1-1-1 delta-sigma modulator to accomplish the spread spectrum function. Fractional-N PLL can achieve high resolution with high operation frequency. The use of digital delta-sigma modulation technique in the fractional-N PLL can eliminate spurs. The SSCG generates clocks at 1.5 GHz, a 5000 ppm down spread with a triangular waveform frequency modulation of 33 KHz. The circuit is fabricated with 0.18 um CMOS technology. The non spread spectrum clocking has a measured jitter of 80 ps and the peak amplitude reduction is 23.44 dB in spread spectrum mode.