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dc.contributor.authorShaw, Jonathanen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.contributor.authorRaza, Hassanen_US
dc.contributor.authorKan, Edwin Chihchuanen_US
dc.date.accessioned2014-12-08T15:09:00Z-
dc.date.available2014-12-08T15:09:00Z-
dc.date.issued2009-08-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2009.2024108en_US
dc.identifier.urihttp://hdl.handle.net/11536/6851-
dc.description.abstractWe study the parametrical yield of memory windows for the metal nanocrystal (NC) Flash memories with consideration of the 3-D electrostatics and channel percolation effects. Monte Carlo parametrical variation that accounts for the number and size fluctuations in NCs as well as channel length is used to determine the threshold voltage distribution and bit error rate for gate length scaling to 20 nm. Devices with nanowire-based channels are compared with planar devices having the same gate stack structure. Scalability prediction by 1-D analysis is found to be very different from 3-D modeling due to underestimation of effective NC coverage and failure to consider the 3-D nature of the channel percolation effect.en_US
dc.language.isoen_USen_US
dc.subjectNanocrystal (NC)en_US
dc.subjectnonvolatile memoriesen_US
dc.subjectprogramming window distributionen_US
dc.subject3-D electrostaticsen_US
dc.titleStatistical Metrology of Metal Nanocrystal Memories With 3-D Finite-Element Analysisen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2009.2024108en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume56en_US
dc.citation.issue8en_US
dc.citation.spage1729en_US
dc.citation.epage1735en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000268282400023-
dc.citation.woscount5-
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