鈦酸鍶作為閘極氧化層之電性與電容量測模型之研究

Abstract

本論文以物理氣相交流濺鍍法成長鈦酸鍶薄膜，控制不同的成長條件包括成長基板溫度、不同氧偏壓、成長氣壓、電漿功率，比較不同成長條件和薄膜厚度的鈦酸鍶薄膜作為閘極氧化層之電性。以鈦酸鍶薄膜製作金屬/絕緣層/半導體 (metal-insulator-semiconductor) 的電容結構，然後量測其電容性質以及漏電流特性。除了探討一般的常見的成長參數對薄膜電性與物性的影響外，並利用氮摻雜與熱處理的方式來改善電容與漏電流性質，在氮摻雜的方式上主要分為兩種方式包括：離子佈植及利用一氧化二氮(N2O)成長犧牲層來造成表面殘餘的氮原子。在電容的量測過程中，發現有嚴重的頻散效應，但文獻上所得的模型都無法有效解決高介電閘極氧化層在電容量測時的頻散效應，於是利用並聯一個電容與消散因子 (dissipation factor)，再串聯量測時不可避免的寄生電阻與電感組成一個包含四個元件的電容量測修正模型，原本電容量測時的頻散現象經由這修正模型校正之後，成功地消除頻散效應，並且利用此修正模型可以得到MIS結構下的損耗正切(loss tangent)，這是在其他相關的研究上很少提到的。

The influences of the processing parameters on physical and electrical properties of SrTiO3 (STO) thin films deposited on Si were investigated. Nitrogen-incorporation method and repeated-spike-heating method were employed to improve the electrical properties of STO for obtaining high capacitance and low leakage current density. The nitrogen-incorporation method can retard the formation of interfacial layers and the repeated-spike-heating method can improve the thermal uniformity of the wafers. We have also developed a four-elements model of MOS capacitor to improve the capacitance-voltage measurement of high-k gate dielectrics. The four-element model includes intrinsic capacitance, loss tangent, series resistance and parasitic inductance, and all elements extracted by measuring the capacitor at two independent frequencies. We can find it always has 20% frequency dispersion of capacitance if the frequency is more than 100 kHz. The frequency dispersion of capacitance is dependent on series resistance and parasitic inductance. Besides, the dissipation factor at 1 MHz is usually 30 times than the corrected dissipation factor.