标题: | 新式金氧半场效电晶体之闸极与源/汲极工程研究 A Study of Novel Gate and Source/Drain Engineering Methods for Metal-Oxide-Semiconductor Transistors |
作者: | 王梦凡 Meng-Fan Wang 黄调元 林鸿志 Tiao-Yuan Huang Horng-Chih Lin 电子研究所 |
关键字: | T型闸极;氮化钛金属闸极;副闸极;销特基能障;鳍状;锗离子布植;T-shaped Gate;TiN Metal Gate;Sub-Gate;Schottky-Barrier;Fin;Ge implant |
公开日期: | 2001 |
摘要: | 在本论文中,我们针对金氧半场效电晶体之闸极与源/汲极部分进行研究,涵盖内容包括基本的复晶矽闸极蚀刻程式建立,自我对准T型闸极电晶体研制,氮化钛金属闸极电晶体之热稳定性,具副闸极(sub-gate)的绝缘层上矽(SOI)电晶体及具副闸极、Fin结构之SOI电晶体的特性研究及利用超浅锗掺杂改善短通道效应等。 我们成功建立一蚀刻复晶矽薄膜程式,适用于不同掺杂种类及浓度的蚀刻,并具有高蚀刻率、均匀性及良好侧图控制(profile control)等。经临界电压、崩溃电荷及电荷泵浦(charge pumping)分析佐证可知,此程式对天线元件仅有少量的损伤,可应用于深次微米元件复晶矽闸极制作。 其次,我们成功研制出一新式可同时形成自我对准T型闸极与空气边壁子(air spacer)的电晶体结构,简称STAIR(self-aligned T-shaped gate and air spacer)。除可有效降低闸极电阻外,空气边壁子的形成对降低寄生电容亦深具潜力。然而制程引起的闸极漏电流将损坏氧化层品质。为此,我们引入氮化矽边壁子大幅降低闸极漏电流,并降低桥接的机率。此结构不仅简单且与传统自我对准金属矽化物(salicide)制程相容,应用于高速元件或高频电路中将深具潜力。 为解决复晶矽空乏效应对元件特性退化的影响,似乎无法避免回归金属闸极结构,然而金属闸极本身亦存在许多问题。我们研究快速退火温度对氮化钛为金属闸极CMOS元件之热稳定性影响。电容-电压结果显示,氧化层厚度及平带电压均受退火温度影响,尤以p-通道元件为甚。此外,在p型电晶体次临界电流特性中观察到隆起(hump)的现象,经分析可知与隔绝区边缘的漏电路径有关。在n型电晶体方面,退火温度提升与通道长度缩减易引起氮化钛膜团块化现象,因而破坏氧化层品质导致闸极漏电流。 我们提出一新萧特基源/汲极SOI场效电晶体结构,系利用一金属副闸极沈积于氧化层上,偏压于副闸极上在通道层感应出汲极(field-induced-drain)。依据偏压模式的不同,同一元件可操作于n或p通道模式且有极佳的开关电流比;对n通道约为107,对p通道可高达108。更重要的一点,电晶体的关闭电流在副闸极适当偏压下显得微不足道。此外,在n通道操作时观察到负微分电导(negative differential conductance, NDC)的现象,成因与大量热电子在氧化层中被捕捉有关。 其次,沿用具副闸极之萧特基源/汲极结构制作Fin SOI场效电晶体,完成90 nm通道长度及50 nm Fin宽度的操作,亦可操作于n或p通道模式下且开关电流比高达108。长通道元件中次临界摆幅随Fin宽度缩减而下降接近60 mV/dec.的理想值。此外,电晶体的导通电流随副闸极偏压的增加而明显上升,主要受到源极端能障变低所致,但副闸极偏压增加却也造成副闸极感应能障下降,而加速临界电压下跌;关闭电流在副闸极适当偏压下亦不明显。p通道操作时,矽化铂较矽化钴有较低的萧特基能障利于电洞穿遂,因此矽化铂较矽化钴有较高的导通电流。 最后,利用低能量与低剂量大角度之锗离子布植源/汲极区域,临界电压与DIBL(drain-induced barrier lowering)等短通道效应明显的被抑制,同时有不错接面漏电流。然而有较差的热载子免疫力。 In this thesis we have investigated several novel methods for gate and source/drain engineering of MOSFETs. These methods include the design of a universal recipe for etching polysilicon layer with different doping types, the fabrication of a novel T-shaped-gate transistor with air spacer. In addition, we have also studied the thermal stability of metal-gated CMOS transistors. Finally, we have also fabricated novel ambipolar Schottky S/D SOI MOSFETs with field-induced drain, and Schottky FinFETs with field-induced source/drain extensions. In closing, the effects of shallow germanium halo implant on the characteristics of nMOSFETs are also investigated. To start with, a universal etch recipe which is capable of anisotropically etching polysilicon gate layers of different doping types and concentrations with high etching rate, superior uniformity and good profile control is successfully demonstrated using a commercial TCP etcher. Only minor plasma induced damage is detected as monitored by the antenna devices, indicating that it is feasible for deep sub-micron CMOS process integration. Next, a novel transistor with self-aligned T-shaped gate and air spacer has been successfully demonstrated, which we dubbed STAIR. The STAIR transistors depict reduced gate resistance, and inherently reduced parasitic capacitance. However, in the original process flow, the gate oxide is exposed during the required long BOE treatment, resulting in large gate leakage. To alleviate this problem, an improved process with the protection of thin nitride layer at the sidewall of poly-Si gate is proposed and proved to effectively reduce the gate leakage as well as bridging probability. The refined process is robust and compatible with salicide processing, which is suitable for future high-speed device and high frequency circuit applications. To solve the device performance degradation caused by Poly-Si gate depletion effect, the use of metal gate seems to be inevitable. However, metal gate technologies possess many issues. In this thesis, we have investigated the thermal stability of CMOS transistors with TiN metal gate. It is found that oxide thickness and flat-band voltage are both affected by rapid thermal annealing temperature, especially for p-channel devices. Moreover, a hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to occur during high-temperature RTA step as gate length becomes smaller, thus, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel devices. In this thesis, we have also proposed and fabricated a novel Schottky-barrier source/drain (S/D) silicon-on-insulator (SOI) MOSFET featuring field-induced-drain (FID) structure, which is controlled by a metal field plate (or sub-gate) overlying the passivation oxide. Depending on the bias polarity, ambipolar operation and excellent on/off current ratio is achieved on the unique device. More importantly, the offset leakage current becomes negligible with the proper sub-gate bias. In addition, the negative conduction (NDC) phenomenon is observed in n-channel operation, which is ascribed to the hot electron trapping during device characterization. Next, we have also applied the FID concept to fabricate a novel Schottky-barrier (SB) FinFET with field induced source/drain extensions. We have successfully demonstrated SB-FinFET with gate length of 90 nm and 50 nm fin width. The new device exhibits superior ambipolar characteristics and high on/off current ratio of 108. In long channel devices, subthreshold slope (SS) approaches the ideal value of 60 mV/dec for narrow-fin-width devices. The output current increases with increasing sub-gate bias, which is presumably due to the tunnel barrier lowering at the source side. The off-state leakage current becomes negligible with the proper sub-gate bias. However, it was found that threshold roll-off is magnified with increasing sub-gate bias, which is probably due to sub gate induced barrier lowering. The silicide material, PtSi with its lower barrier height for holes further enhances the output current, compared with using CoSi2 in p-channel operations. Finally, we have investigated the use of shallow germanium halo doping on improving the short channel effects of deep-submicron n-channel MOSFETs. We demonstrate that the incorporation of such a shallow Ge halo implant is effective in improving threshold voltage roll-off and drain-induced barrier lowering, while maintaining a low junction leakage. However, hot-carrier degradation dose not seem to be improved by Ge halo implant. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT900428141 http://hdl.handle.net/11536/68829 |
显示于类别: | Thesis |