雜湊函數sha-1之硬體設計與實現

Abstract

用於網路安全機制的密碼演算法其運算處理速度在近年來的研究領域中越來越受到重視。然而，過去的研究成果顯示出以軟體設計實現的架構不論在加解密或是認證方面其效能可謂相當低落，以至於無法滿足現實環境的需要。近年來越來越多的跡象顯示網路安全的應用架構(如，企業內部虛擬網路)其高速處理密碼演算加速器日益受到重視以及關注。因此，在這篇論文中我們將顯示，建構一個以硬體為設計與實現基礎的密碼演算法加速器(如HMAC賴以為基礎的雜湊函數SHA-1)是合理且必要的。我們所提出的”五組內部平行執行單元組”的嶄新架構將提供雜湊函數SHA-1極佳的效能，其表現與現今商用產品不惶多讓。

The processing speed of cryptographic algorithms in IP Security (IPSec) has received much attention in recent research, and it has been shown that software design and implementation performs poorly in either encryption or authentication. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as Virtual Private Networks (VPN). Hence, as we shall show in this thesis, it’s necessary and reasonable to construct cryptographic accelerators using hardware design and implementation of HMACs based on a hash algorithm such as SHA-1. The novel architecture we proposed, five internal parallel-execution entities, leads to a supreme performance as well as the commercial products nowadays.