電容式微加速度計系統及感測電路之設計、分析與模擬

Abstract

本論文主要以研究電容式微加速度計系統及系統後段之感測電路為主，論文中分別對系統架構及電路做分析。在系統架構方面，我們使用Sigma-delta架構做微加速度計的系統架構，其優點為可利用閉迴路來做靜電力迴授，並且輸出為數位訊號及具有很高的訊雜比，可大幅減少量化雜訊對系統的影響，另外由分析中可以知道降低阻泥係數或增加彈簧係數與質塊質量來增加品質因子或使用真空封裝來降低Brownian 雜訊的影響，此兩種雜訊經過減少後，與電路雜訊相比將可忽略。在感測電路方面，我們說明兩種常見的感測電路，並且說明電路上的不理想特性及來源，以及如何改善，經由分析後得知使用改良後切換式電容電路來做為感測電路(CDS)方式比較好，因為可消除電路上不理想特性而剩下放大器熱雜訊無法消除，不過CDS需配合一組複雜之時序產生器，做為每個開關切換的依據，另外為了提高電容量測之精確度，必須將熱雜訊作最佳化。本論文最後建構整個電容式微加速度計之系統做動態模擬，調整各各參數並做比較，驗證模擬與理論分析結果相同，電路模擬方面，以切換式電容電路做靜態之模擬，由於開關誤差影響，因此與理論有些許誤差。另外我們設計一個頻寬為57M Hz運算放大器以及204K Hz的振盪器及一組時鐘產生電路並驗證其功能為正確，本論文之目標為設計輸入為±5g之加速度輸出需為±5V之系統，模擬結果可得知在取樣頻率為100K Hz下，輸入在±4.7g內可正確得到相對輸出值，輸出誤差最大為0.1V。

The present dissertation studies the system architecture and sensing circuits of a capacitive micro-accelerometer. Sigma-delta concept is used as the system architecture of micro-accelerometer for the purpose of high S/N ratio, digital output and closed-loop electrostatic feedback. Furthermore, by reducing damping coefficient or increasing spring coefficient and proof mass, we are able to produce high quality factor. By using vacuum packaging, we can further reduce Brownian noise. Note that when reducing the effects of these noises, the remaining noises compared to circuit noise can be neglected. Two common used circuits are analyzed in the sensing circuit with the presence of the non-ideal characteristics of the circuits. By performing a series of analysis, we have used a modified version of corrected double sampling to reduce non-ideal circuit characteristic except thermal noise. In order to increase sensing resolution, we performed the optimization to the Op amp thermal noise. Finally, we are able to develop a capacitive micro-accelerometer system model for the purpose of simulating the dynamic behavior. Note that with the model, we are able to compare different systems by tuning its corresponding parameters. Here, we verified that the analysis result is closed to the theory. For the switch capacitor circuit, due to the switch error effect, the result has experienced a 5% difference than theory. An operational amplifier with a 57M Hz unit-gain bandwidth, and a 204K Hz frequency of oscillator and a clock generator were designed and verified. The object of this dissertation is to design a ±5g input which has a ±5v output voltage. The simulation result show that at 100K Hz sampling frequency, the system possesses correct output signal when input signal is in the range of ±4.7g, and the output signal has a 0.1v maximum error.