IEEE 802.11n 基頻接收機設計與實現

Abstract

IEEE 802.11n被視為是下一代高速無線通訊的規格。其基頻的主要特性是利用多重輸入輸出正交分頻多工(MIMO-OFDM)技術。在本論文中，針對IEEE 802.11n接收機做設計與實現(以TGn Sync的提案為準)。我們將接收機分為前端與後端兩部分。前端的部分包括了封包偵測、自動增益控制、頻率偏移估計、碼框偵測、通道估計與快速傅利葉轉換等模組。而後端的部分則包括了最小均方誤差檢測(MMSE Detection)，軟性位元反對應(soft-bit demapper)與維特比解碼器(Viterbi Decoder)。在此我們設計了接收機的前端並對整個接收機做系統模擬。根據FPGA的設計流程，我們實現了2×2的前端接收機。在這個設計之中，我們用了座標旋轉數位電腦(CORDIC)等技術來做相位的估計與旋轉，也針對封包偵測與頻率偏移估計提出了有效的架構。由模擬圖可看出我們的在隨機產生的MIMO通道之下表現正確。

IEEE 802.11n is known as the specification for the next generation high-speed WLAN systems. The distinct baseband feature is the use of multi-input multi-output (MIMO) OFDM technology. In this thesis, we consider the design and implementation of an IEEE 802.11n baseband receiver (with the TGn Sync proposal). We divide the receiver into the front-end and the back-end receiver. The front-end receiver includes modules of packet detection, automatic gain control, frequency offset estimation, frame detection, channel estimation, and fast Fourier transform (FFT). The back-end receiver includes modules of the minimum mean square error (MMSE) signal estimator, the soft-bit demapper, and the Viterbi decoder. We first design the front-end receiver and perform system simulations for the whole receiver. Using the FPGA design flow, we then implement the front-end receiver for a 2x2 system. In the design, we use the CORDIC algorithm for phase estimation and rotation and propose efficient structures for packet detection and frequency offset estimation. Simulations show that our design perform properly in random generated MIMO channels.