半導體廠提高達交率的派工法則

Abstract

「達交率」指的是總產出批量中準時達交批量所佔的比例，如何有效的提高達交率是目前半導體產業非常重要的課題，過去十分缺乏以提高達交率為主要目標的研究。 本研究以發展提高半導體廠達交率的派工法則為目標，首先將各種傳統派工法則以模擬實驗做達交率的績效驗證，再根據表現最好的關鍵比值法（CR）加入新的觀念發展新派工方法。本研究提出了三種新的觀念以改進關鍵比值法，並將各種新的派工方法、傳統的派工方法及相關文獻所提出的派工方法進行模擬實驗加以比較驗證，為求實驗的客觀性，本研究的模擬實驗將同時在不同的產品組合及工廠負荷情境下進行，依據模擬結果顯示，本研究所提出的遲交比例加權法（DCR）的達交率績效明顯優於其它派工法則並且績效穩定。

Hit rate, the rate of on-time delivery, recently becomes a very important performance index in semiconductor foundry fabs. Yet, previous studies on lot dispatching focused on some other relevant performance indices, but very few directly focus on the raising on hit rate. This research aims to develop dispatching algorithms for raising the hit rate of semiconductor fabs. Some popular dispatching rules are first examined by discrete event simulation. Results show that CR (critical ratio) dispatching rule exceeds the others. This research proposes three novel perspectives to enhance the CR dispatching rule. The hit rate performance of the enhanced-CR rules and some significant dispatching rules in literature are compared by simulation, in scenarios varying in product mix and fab loading. Simulation results show that DCR（delay critical ratio）, one of the enhanced-CR dispatching rules, outperforms the others.