襯層在深次微米金氧半導體積體電路製造的應用與影響

Abstract

為了改善金氧半導體(MOS)元件的可靠性，在積體電路的製造過程中，在不同的站別常會使用到襯層。襯層可以用來作應力減輕的緩衝層、材料黏著力的改善層或者是擴散阻障層。所使用的襯層材料視製程、元件的需求，包括了金屬與介電質材料。 在使用鎢栓的製程中，鈦金屬是最常被用來做金屬鎢的黏著力改善層。當元件的尺寸縮小到次微米時，栓篩的縱橫尺寸比(Aspect Ratio)變大，因此為了要鍍好鈦金屬膜，各種鍍膜方式相繼被提出，其中最被業界廣為接受的有: 準直鈦(Collimated-Ti) 和金屬電漿離子鈦(ion-metal plasma –Ti)。本研究探討準直鈦(Collimated-Ti) 和金屬電漿離子鈦(ion-metal plasma –Ti)對金屬連接(via)阻值的影響。從掃瞄式電子顯微鏡的影像可知，IMP-Ti膜的晶粒較CO-Ti膜大。實驗結果發現IMP-Ti膜和CO-Ti膜的電阻係數會隨膜厚度而改變。IMP-Ti膜因晶粒較大，因此，具有較低的反射率和較低的電阻係數。使用IMP-Ti做黏著力改善層的元件，其via阻值比使用Co-Ti做黏著力改善層的元件高出13.6%。從實驗結果分析可知，元件via阻值的差異主要是來自使用不同的黏著力改善層。 對使用低介電常數材料當介電層的元件，介電質襯層常被用做阻障或保護層。本研究探討介電質襯層的厚度對使用低介電常數HSQ當介電層之導線電容的影響。實驗結果發現以HSQ當介電層之導線電容比使用一般二氧化矽的導線電容低20-27%，而參雜氟的二氧化矽可降低6-16%的導線電容。就金屬間(intraline)的電容而言，介電質襯層的厚度在寬的金屬線/窄的金屬間距條件下，效應最顯著，當金屬線的寬度固定時，隨著金屬間距的增加，介電質襯層的厚度對intraline電容的效應將會減低。較厚的介電質襯層會導致較高的intraline電容。而介電質襯層厚度對金屬線間(interline)電容的效應則被介電層厚度之差異所掩蓋而變的不明顯。介電層厚度之差異對via阻值有很大的影響，因此，對0.18微米以下的製程，介電層化學機械研磨的控制變的很重要，因為它決定著介電層的厚度。 由4-乙烷氧基-甲烷(TEOS)經電漿加強化學氣相沉積(PECVD)的二氧化矽，是業界常用來做介電質的材料。當TEOS沉積到元件時，會遭遇三種不同的材質: 氮化鈦(TiN)，金屬鋁(Al)和二氧化矽(SiO2)。本研究探討TiN ，Al和SiO2 三種不同的襯層對TEOS 階梯覆蓋率(step coverage)的影響。實驗結果發現沉積初期，TEOS在SiO2 襯層的沉積速度最快； TEOS在TiN襯層有最佳的側壁step coverage。而因Al襯層表面粗糙，使得TEOS在Al襯層上的step coverage最差。不同的襯層亦會影響TEOS在底部(bottom)的step coverage，但不論使用何種襯層，TEOS 的bottom step coverage 都比sidewall step coverage好。 在0.18微米以下的元件，通常都使用淺溝槽絕緣法(Shallow Trench Isolation, STI)來絕緣MOS。本研究探討沉積STI 膜時，發生圓形缺陷的機制。並探討襯層對此圓形缺陷的影響。實驗結果發現使用氮氧化矽(oxynitride) /二氧化矽(oxide)的複合襯層，不僅可以消除圓形缺陷，亦可以增加STI絕緣的強度。oxynitride / oxide的複合襯層可以使STI絕緣的強度增加30~375%，亦使STI絕緣的均勻度從大於200% 改善到小於10%。

To improve the reliability of MOS devices, various liner films have been applied to different stages of the integrated circuit manufacturing processes. A liner layer can be used as a stress-release buffer film, a adhesion promoting layer, or a barrier layer to prevent harmful diffusion. The used liners include metallic and dielectric materials depending on the process demands. In the tungsten plug process, titanium liner is a well-known glue layer. When the device size scales down to beyond sub-micron, the aspect ratio for the tungsten plug process increase. To fill the high aspect-ratio plugs, various titanium deposition processes have been presented. Both collimated titanium(CO-Ti) and ion metal plasma titanium (IMP-Ti) are the widely used materials for plug liner layers. The reasons for the different vias resistance between Co-Ti and IMP-Ti processes are explored in this research. The scanning electron microscopy (SEM) images show that the IMP-Ti film has larger grain size than that of CO-Ti film. The resistivity of IMP-Ti and Co-Ti will change with their thickness. We conclude that the lower reflectivity and resistivity of IMP-Ti films are caused by the fact that IMP-Ti has a larger grain size than that of CO-Ti films. The electric measurement of vias resistance shows that the vias using IMP-Ti as the plug liners give 13.6% higher via resistance than those using Co-Ti as the plug liners. From the experimental data, we conclude that the titanium glue layer is the dominant factor for the difference in via resistance. Dielectric liners were often used as the barrier and passivation layer for using low dielectric material as the interlayer level dielectric. The liners' thickness effects on the electrical performance of hydrogen silsesquioxane (HSQ) as the interlayer level dielectric (ILD) has been determined by using two-metal-layered test structures. In comparison with SiO2, HSQ test structures formed with SiO2 cap and liner or with SiO2 cap only, have 20-27% lower intraline capacitance while 6-16% reduction was observed for fluorosilicate glass (FSG) relative to SiO2. The liner thickness effect on the intraline capacitance was most obvious for the wide metal / narrow spacing (0.46 µm/0.23 µm) condition. When the metal width was kept constant, the liner thickness effect on the intraline capacitance was reduced for increasing metal spacing. The thicker liner gave larger intraline capacitance. The liner thickness effect on the interline capacitance was eliminated by the variation of SiO2/HSQ/SiO2 stack thickness after oxide Chemical Mechanical Polishing (CMP). This thickness variation also has a strong impact on landed/unlanded via resistance. Therefore, a good control of oxide CMP on the ILD stack is needed to reduce the thickness variation of the liner/HSQ/cap ILD stack which in turn will enhance process yields in the 0.18 µm devices. Plasma enhanced-chemical vapor deposition (PECVD) tetraethylorthosilicate (TEOS) films are extensively used as the interlayer dielectric films in multilevel interconnection processes. When TEOS oxide films were deposited on metal patterns, three different substrates, titanium nitride (TiN), aluminum (Al) and oxide (SiO2) were encountered. The different liners including TiN, Al and SiO2 are used to examine the dependence of these liners on TEOS step coverage. The deposition rates of TEOS oxide revealed that the SiO2 liner lead to highest TEOS deposition rate during the initial deposition period of 5 sec. The TiN liner exhibited the highest sidewall step coverage of the TEOS oxide. The TEOS oxide sidewall step coverage using Al liner was deteriorated due to Al's granular surface. Additionally, different liners exhibited different coverage of the bottom step. Moreover, the bottom step coverage exceeded the sidewall coverage for all liners. Shallow trench isolation (STI) is extensively used as the isolation method beyond 0.18um generation. This study explored the formation of circular defects in high-density plasma (HDP) STI deposition. Besides this, the liner effects on the circular defects are also studied. Experimental results showed that the oxynitride / oxide composite liner eliminated the circular defects. Additionally, the oxynitride / oxide composite liner also improved the breakdown strength of the STI oxide. The breakdown strength of the STI oxide increases respectively 375%, 30% in the wafer center and edge. The uniformity of the STI breakdown strength was reduced from >200% to less than 10% using the composite liner.