適用於雙頻帶接收機前端電路之共電流低雜訊放大器和低電壓微混頻器

Abstract

本論文的第一部份分三個方面研究共電流雙頻帶低雜訊放大器電路設計方法，包含輸入匹配，雜訊指數，和功率消耗，並且以電路元件來表示這些特性。實作的共電流雙頻帶低雜訊放大器顯示在2GHz和5.25GHz分別有7.45 dB和6.06 dB的增益，-12.8 dB和-12.9 dB的輸入返回損耗，3.54 dB和4.80 dB的雜訊指數，並且僅消耗7.21mw的低功率損耗。第二部份針對採用偶次諧波混頻器而只需單一頻率合成器的新式共電流雙頻帶接收機架構實作共電流雙頻帶接收機前端電路。此電路在2.45GHz和5.25GHz分別達到17.2 dB和11.8 dB的電壓增益，-15.9 dB和-15.8 dB的射頻端輸入返回損耗，及-21.0 dBm和-15.3 dBm 的P1dB。第三個部份是操作在1V的2.45GHz低電壓微混頻器。此電路在1.72mw的低功率消耗下有14.9 dB的射頻端輸入返回損耗，8.28 dB的轉換增益，-5.63 dBm的P1dB和4.21 dBm的IIP3。本論文中的三顆晶片均使用標準0.18um CMOS製程設計和實作，並且在國家晶片系統設中心完成量測。

In the first part of the thesis the design method of concurrent dual-band LNA topology is studied and analyzed in three respects, including input matching, noise figure, and power dissipation. These characteristics are expressed in terms of circuit elements. The implemented concurrent dual-band LNA demonstrates 7.45 dB and 6.06 dB power gain, -12.8 dB and -12.9 dB input return loss, 3.54 dB and 4.80 dB noise figure at 2GHz and 5.25Gz, respectively, with low power consumption of 7.21mw. In the second part a concurrent dual-band receiver front-end for wireless LAN 802.11a/b/g applications is implemented base on the new concurrent dual-band receiver architecture which needs only one frequency synthesizer by employing sub-harmonic mixer. It achieves 17.2 dB and 11.8 dB voltage gain, -15.9 dB and -15.8 dB RF port input return loss, -21.0 dBm and -15.3 dBm P1dB at 2.45GHz and 5.25GHz, respectively. The third part is the 2.45GHz low-voltage micromixer for 1V operation. It has 14.9 dB RF port return loss, 8.28 dB conversion voltage gain, -5.63 dBm P1dB, and 4.21 dBm IIP3 with 1.72mw low power dissipation. The three ICs in this thesis are all designed and fabricated using CMOS 0.18um process and measured in National Chip Implementation Center (CIC).