分析4/6層印刷電路板貫孔結構的電感特性

Abstract

隨著電子技術不斷進步，時序脈波信號愈來愈快，電磁干擾問題也日益嚴重。在多層電路板中，通常具有專屬的電源層與接地層作為系統電源與信號回流路徑之用。而地彈雜訊（Ground Bounce）是電源系統產生傳播電磁干擾的主要機制。要抑制地彈雜訊通常使用去耦合電容，但去耦合電容有寄生電感會影響去耦合電容的高頻性能。 本論文使用HFSS分析幾種不同的貫孔結構，找出其等效電感值，並探討如何降低貫孔結構的等效電感值。

With fast increase of clock frequency, the high frequency noise on power distribution network caused by ground bounce is a primary source of electromagnetic interference (EMI) and signal integrity. In multilayer printed circuit boards, it is prevalent to use dedicated power／ground plane pair(s) for power delivery network. The decoupling capacitor is to usually employed suppress the ground bounce, but its intrinsic inductance and parasitic inductance associated with the mounting structure used affect the capacitor’s decoupling performance at high frequencies. In this thesis, we use HFSS to analyze several different kinds of vias structures to find out its equivalent inductance value. We also discusses how to reduce the equivalent inductance value of vias structure.