LDMOS功率元件特性分析及可靠性研究

Abstract

近年來，高功率積體電路興起並有廣泛的應用，而具有平面結構的LDMOS（平面二次擴散之金氧半場效電晶體）有高度整合性，於焉成為主要的驅動元件。LDMOS特有的低參雜區域能提供大電阻，是其能耐高壓的原因。在設計LDMOS時，能同時擁有低的開啟電阻以及高耐壓為重要的訴求點。 本篇論文的內容探討LDMOS的特性，包括基本電流-電壓特性、崩潰機制、與崩潰機制有關的重要製程參數、可靠性分析、以及SPICE模型的建立。其中，基本特性與崩潰機制是使用TCAD的模擬分析；而可靠性研究是利用常溫下熱載子加壓(stress)的實驗分析。SPICE模型是將既有的MOS模型加上可變電阻針對線性區域做模擬。 根據我們的研究，可以做出以下的結論：欲同時擁有低開啟電阻以及高耐壓是互相抵觸的；on-state的崩潰電壓由drift region內橫向電場決定，而off-state則是由bird’s beak下方的能帶彎曲程度決定；drift region濃度以及閘電極延伸的長度對崩潰電壓有很大的影響；NLDMOS與PLDMOS在常溫下用熱載子stress後皆會產生電子缺陷（electron trap）；最後，LDMOS在線性區域的HSPICE模型是利用考慮閘電極延伸區域下方的電子濃度來建立的。

High voltage integrated circuits are emerging in a wide variety of application nowadays. LDMOS (Lateral Double-Diffused MOSFET) is usually the driver component in these circuits, thanks to its planar structure. The lightly-doped drift region provides a large drain resistance, allowing to withstand the high-applied voltage. One of the main objectives in designing LDMOS devices is to minimize the on-resistance while still maintaining a high breakdown voltage as well. In our study, we will engage in the characteristics of LDMOS, including the I-V curve discussion, the breakdown mechanism, some of the key specific parameters related to breakdown voltage, the reliability issues after hot carrier stress and the quasi-saturation effect. Finally, a spice model is developed. In addition, the investigation of basic I-V characteristics and breakdown mechanism are carried out by TCAD simulation. On the other hand, the hot carrier stress reliability issue is examined experimentally. The spice model is constructed by adding a variable resistance to a standard MOSFET model. According to our study, we can conclude that: low Ron and high breakdown voltage are trade-off; on-state breakdown voltage is determined by the electric field in the drift region while off-state breakdown voltage is determined by the surface band bending at the bird’s beak; drift region concentration and gate extension length have significant influence on breakdown voltage; NLDMOS and PLDMOS both have electron taps after stress; finally, HSPICE model of LDMOS at linear bias can be developed by considering the electron concentration in the gate extension region.