適於數位訊號處理器之低功率多存取埠多存取埠設計

Abstract

A low power multiple access port register file suitable for parallel processing processor is proposed in this paper. New register file cell, read/write port architecture and low power circuit design techniques are used in register file design. Static noise margin under the constraint of multiple access ports is discussed and method to maintain static noise margin is proposed. All the results are simulated in TSMC 100nm CMOS technology. A maximum 5X leakage reduction is achieved by using Dual-Vt transistors in the register file cells and 2X energy saving by adjusting the size of the strong inverter compared to normal register file cell design. An optimum sizing ratio is found to trade off between energy consumption and transistor size. Buffer insertion and way to cope with interconnections are also examined in this thesis. Register file architectures for difference types of processors are also proposed and examined in chapter 5. Register file compiler design considerations and testing issues are also address in chapter 5. A 4W8R 16word 32 bit register file which occupies 1x1 silicon area is implemented. The register file consumes 2mW when 32 bit data are written into the register file in the critical case and clock runs at 2GHz. The load store operation can be completed with one clock cycle. Metal routing and access ports occupy the major part of the overall layout. Low power register file cell and single-ended Read/Write ports are used to reduce power consumption and is especially useful in nano-scale CMOS technology.

A low power multiple access port register file suitable for parallel processing processor is proposed in this paper. New register file cell, read/write port architecture and low power circuit design techniques are used in register file design. Static noise margin under the constraint of multiple access ports is discussed and method to maintain static noise margin is proposed. All the results are simulated in TSMC 100nm CMOS technology. A maximum 5X leakage reduction is achieved by using Dual-Vt transistors in the register file cells and 2X energy saving by adjusting the size of the strong inverter compared to normal register file cell design. An optimum sizing ratio is found to trade off between energy consumption and transistor size. Buffer insertion and way to cope with interconnections are also examined in this thesis. Register file architectures for difference types of processors are also proposed and examined in chapter 5. Register file compiler design considerations and testing issues are also address in chapter 5. A 4W8R 16word 32 bit register file which occupies 1x1 silicon area is implemented. The register file consumes 2mW when 32 bit data are written into the register file in the critical case and clock runs at 2GHz. The load store operation can be completed with one clock cycle. Metal routing and access ports occupy the major part of the overall layout. Low power register file cell and single-ended Read/Write ports are used to reduce power consumption and is especially useful in nano-scale CMOS technology.