高效能及低功率維特比解碼器的設計和實現

Abstract

隨著時代的進步，移動式和無線式的系統變得愈來愈重要。因此，低功率的電路設計成為整個系統設計的重要考量。在多數移動式和無線式的系統中，維特比解碼器占據大量的計算量。所以，減少維特比解碼器的計算量可以有效的降低整個系統的功率消耗。然而，多數的設計者僅在產出量和功率消耗間取得平衡。這種的做法並不能滿足高產出量且低功率的應用。因此，我們提出一個擁有路徑融合和預料技術的維特比解碼器。在路徑預料技術上，超過成9成殘餘路徑可以事先預測。路徑融合的特性能減少7成以上記憶體的存取。如此的設計，不單單只有更正能力的考量，而且提供高產出量且低功率的解答。測試驗証的晶片採用0.35um 1P4M CMOS的製成。測試驗証的晶片能夠達到133Mb/s的產出量，而且在66Mb/s的產出量時僅擁有低於55mW的功率消耗。

The mobile and wireless systems become more and more important these years. Therefore, a low power design is the main issue of the overall system. In lots of mobile or wireless systems, the computing complexity is concentrated in the Viterbi decoder. So, to reduce the computing complexity of the Viterbi decoder is equivalent to reduce most of the power consumption in overall communication system. However, most designers trade the throughput rate for power consumption. This kind of the designs can't satisfy the high data rate application nowadays. Thus, we propose a 133Mb/s, 64-state, radix-4, 16-level soft decision Viterbi decoder with the path merging and prediction techniques. In the prediction algorithm, over 90\% survivor path can be forecasted. And, the memory access reduces more than 70\% on the average with the aid of path merging property. Thus the proposed design not only considers the error correction capacity, but also provides a high speed and low power solution. A test chip is fabricated in 0.35 $\mu m$ 1P4M CMOS process, and can achieve the maximum throughout rate of 133Mbit/s under 3.3V. The measured power consumption is below 55mW under 66Mb/s throughput rate at 2.2V.