LPGC:一個基於最佳閘控制時脈拓樸結構之新穎的低功耗電路擺置演算法

Abstract

本論文研製之電路擺置器，乃基於將用於低功耗設計下之閘控制時脈網路之功率消耗最佳化。首先，基於考慮時脈網路之實體設計連線關係及將其切換機率最小化，先建製一個最佳化閘控制時脈拓樸結構。再透過新穎的評估函數，本論文研製之擺置器可提供讓最佳化閘控制時脈拓樸結構成為可繞結構之適當電路擺置。本擺置器可提供專為低功耗時脈網路繞線演算法之專用電路擺置，這是因為本擺置器提供該演算法將積體電路連線功耗最小化之全域最佳化解。積體電路連線之功耗是一項在奈米製程技術下的嚴重問題。實驗結果證明本擺置器可將閘控制時脈網路功耗減少至少25%。

In this thesis, a placer based on optimizing the power consumption of clock gating network is presented. First, we construct an optimal gated clock topology based on considering the physical connectivity, and minimizing the total switching activity of the clock network. Then, with a novel measure function, our placer can build a suitable placement solution which makes the optimal gated clock topology being routable. Our placer can give a dedicated placement seed to any low power gated clock routing algorithm since we provide them a global optimized solution for reducing the interconnect power which is a severe factor in the coming nano-scale era. Experimental results show that our placer indeed works and can help gated clock routing algorithms to additionally save power consumption by 25%.