積體整合化CMOS 5.25GHz射頻收發器前端電路和2.45 & 5.25GHz共電流雙頻帶低雜訊放大器

Abstract

在這篇論文研究中，主要討論兩個主題；第一個主題是CMOS整合射頻收發器前端電路，內容為整合一個傳送/接收開關，一個低雜訊放大器，和一個功率放大器在單一晶片上，並操作在高頻5.25GHz。此射頻前端電路單一全整合晶片中包含一個介入損耗為5.5dB的傳送/接收開關，和一個功率增益為10.7dB，雜訊指數為4.68dB，IIP3為0dBm的低雜訊放大器，和一個輸出1dB功率壓縮點為11dBm，功率增益為7.5dB的功率放大器(量測值)。為了達成單一晶片和系統單晶片的設計目標，此前端電路完全未採用晶片外元件做為匹配的設計以便日後和其他電路整合。射頻收發器前端的工作模式可經由傳送/接收開關的控制電壓切換傳送和接收兩種模態。另一主題為CMOS雙頻帶2.45和5.25GHz低雜訊放大器。此電路亦全使用晶片內的元件達成高整合度的目標。放大器在2.45GHz的功率增益為5.78dB，雜訊指數為4.7dB，IIP3為7dBm，在5.25GHz的功率增益為3.24dB，雜訊指數為5.69dB，IIP3為17dBm，且此量測結果和模擬結果相去不遠。為了減少低雜訊放大器電晶體從矽基板所耦合的雜訊，我們使用雙閘極電晶體當作放大器的電晶體。以上兩組晶片皆以台積電CMOS 0.25-μm 的製程實現並完成量測和模擬比較討論。

This thesis contents two works. First, we implement a fully integrated CMOS RF front-end including a T/R switch, a LNA, and a PA for 5.25GHz application. The single chip front-end circuit consists: a 5.5dB insertion loss transmit/receive switch (T/R sw), a 10.7dB power gain, 4.68dB NF, 0dBm IIP3 low noise amplifier (LNA), and a 11dBm Pout-1dB, 7.5dB power gain power amplifier (PA) (experimental results). To achieve single chip design target, this chip was designed without any off-chip matching component. The front-end circuit was designed for two operation modes: transmission mode (TX) and receiving mode (RX). We can switch two operation modes by changing the control voltage of the T/R switch. Second, we will describe the topology and concepts of the dual-band receiver. Furthermore, we have completed a concurrent dual-band LNA for 2.45GHz and 5.25GHz operation. The LNA has a 5.78dB gain, 4.7 NF, 7 dBm IIP3 at 2.45GHz and 3.24dB gain, 5.69 NF, 17dBm IIP3 at 5.25GHz (experimental results). The simulation and measurement results comparisons are close. We use dual-gate MOSFETs to reduce the coupling noise from the Si-substrate. These two IC have fabricated in a TSMC 0.25-μm CMOS technology. Moreover, the measurement and comparison with simulation had been done.