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dc.contributor.author黃文傑en_US
dc.contributor.authorWen-Chieh Huangen_US
dc.contributor.author陳昌居en_US
dc.contributor.authorChang-Jiu Chenen_US
dc.date.accessioned2014-12-12T02:32:10Z-
dc.date.available2014-12-12T02:32:10Z-
dc.date.issued2002en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT911706007en_US
dc.identifier.urihttp://hdl.handle.net/11536/71303-
dc.description.abstract由於積體電路製程技術的快速進步,已使得單晶片系統,或稱系統晶片 (System-on-Chip, SoC) 可以將無線通訊、網路電腦、或消費性電子、整個系統實現在一矽晶片上,而且在系統晶片趨勢下,晶片中的電晶體數量未來將以倍數成長。因此這些系統晶片將必須是省電、含有高速處理能力的RISC CPU core、特殊用途之 DSP core或 Network processor於其中。如此複雜之系統晶片本身與其應用系統 (含軟硬體) 的發展必須要有一個良好的設計環境,包括Electronic Design Automation工具、Hardware-Software Co-design工具、以及驗證測試工具。首要之務在於如何應用電腦輔助設計及驗證測試等相關技術至系統晶片的設計、以及通訊IC(含類比、數位及混訊積體電路)之設計上,以爭取市場時效 (Time-to-market)。軟體/硬體相互驗證系統正是為了希望能解決這個問題。如何利用既有的基本元件驗證程式與樣本,搭配EDA工具的幫忙,運用軟體模擬器在速度上的優勢,結合硬體模擬器的優點,在軟體與硬體相互配合與運作的情況下,能大幅的提升系統晶片的驗證與功能上的測試,改善傳統晶片設計上的的缺陷。 在本文中將使用智原科技的DSP(FD216)[8]與一些元件和智原科技DSP驗證樣本與測試程式,使用一個最系統晶片的設計方法,讓軟體和硬體工具配合Seamless[1](明導科技的EDA工具),提供一個靈活的系統晶片相互驗證實作方法,並將系統晶片設計中較複雜的運算與負荷最重部分交由軟體來模擬,而有關系統晶片電路訊號與周邊接腳的處理,則由交由硬體模擬器來分擔,並與原來的RTL程式碼做效能上與功能上的比較,並成功的通過驗證。且在軟體硬體同時運作下,平均在執行測試程式的速度上可以達到70倍的差距,如果純粹以軟體最佳化來模擬,更可以縮短到500倍以上的時間差距。zh_TW
dc.description.abstractAs the semiconductor technology has made great progress, System-on-Chip has become the kernel technologies for integrating computer, consumer, and communication. In other words, a system, which consists of CPU cores like RISC or DSP, memories and other IPs, can be easily embedded into a chip. But to make a SoC product successful, we must take care of the integration of hardware and software. Thus, it is quite critical that to build the HW/SW co-verification environment with EDA tools, HW/SW co-design tools, and other technologies to shorten the development cycle of SoC. The HW/SW co-verification system utilizes EDA tools, the features of various IPs, and hardware simulators, combining with the fast software simulation to improve the testing flow and the simulation performance. In this thesis, we build a HW/SW co-verification environment with innovative methods to speed the HW/SW simulation performance by integrating Faraday's DSP core [8], the test benches, and the Seamless [1] tool. In our HW/SW co-verification system, the software part will execute the computation-intensive part and the hardware will be responsible for the signal communication. The experiments have shown that our HW/SW co-verification system have a great improvement in the simulation performance over 70 times than the traditional method.en_US
dc.language.isozh_TWen_US
dc.subjectSoCzh_TW
dc.subject軟體/硬體zh_TW
dc.subject相互驗證zh_TW
dc.subjectSoCen_US
dc.subjectSoftware/Hardwareen_US
dc.subjectCo-Verificationen_US
dc.subjectVerificationen_US
dc.titleSoC 軟體/硬體相互驗證系統zh_TW
dc.titleSoC Software/Hardwaer Co-Verification Systemen_US
dc.typeThesisen_US
dc.contributor.department資訊學院資訊學程zh_TW
Appears in Collections:Thesis