互補式金氧半低功率十位元20MHz取樣頻率脈管式類比數位轉換器之設計與分析

Abstract

本論文中,將設計與分析一個十位元,20MHz的取樣頻率低功率互補式金氧半脈管式類比/數位轉換器.為了同時達到低功率和高速運作,本設計採用每級1.5位元的架構並運用數位錯誤修正的技術在這個類比/數位轉換器中.整個電路是由九級加上一個前端輸入取樣保持電路所組成,功率消耗僅25 mW.為降低功率消耗,使用一些電路技巧: 一個不易受元件匹配影響的動態比較器,一個不消耗靜態功率的參考電壓電容分壓器,一個消耗2.6 mW、高速、新的兩級架構運算放大器. 此轉換器使用台積電0.25μm 1P5M 互補式金氧半的製程製造.整個晶片佈局的面積是1974x1751 μm2.輸入範圍為 ±1V,2.5V的操作電壓.量測的結果其差動非線性度(DNL)在0.6/-0.8 LSB之間,積分非線性度(INL)在6.5/-1.5 LSB之間.在1MHz的輸入訊號且取樣頻率在20MHz的情況下,信號對雜訊及諧波比值(SNDR)為42dB.

In this thesis, a 10-b 20MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is design and analysis. The 1.5b/stage architecture with digital error correction is used in this ADC for low-power and high-speed considerations. The prototype ADC is implemented by an input sample and hold circuit (S/H) and 9 identical unscaled pipelined stages. The power dissipation of the analog part is only 25 mW. Some circuit techniques are used to achieve low power dissipation. It includes the mismatch insensitive dynamic comparator, a capacitive reference voltage divider and a new low-power two-stage opamp. The ADC is fabricated with TSMC 0.25um 1P5M n-well CMOS technology. The total layout area is 1974x1751 μm2. Input range of the ADC is ±1 V with 2.5 V supply voltage. Measured performance includes 0.6/-0.8LSB of DNL, 6.5/-1.5LSB of INL, 42dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 1 MHz input at 20 MS/s.