標題: | A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection |
作者: | Wang, Chung-Yi Wu, Jieh-Tsorng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Analog-digital conversion;calibration;clocks;phase estimation;time-interleaved;timing circuits;timing skew |
公開日期: | 1-六月-2009 |
摘要: | This paper describes a timing-skew calibration technique which equalizes the phase spacings among multiphase clocks. The scheme uses simple sample-and-hold circuits controlled by the multiphase clocks to sample a common reference input. Phase spacing is measured by counting the number of zero crossings between two adjacent sampling sequences. A zero-crossing detection scheme is proposed. It has better immunity against the offsets of the comparators used in the detector. A digital calibration processor is also proposed. It examines the outputs from the zero-crossing detectors, and then adjusts the delays of clock buffers in order to minimize timing skews. The proposed calibration scheme does not demand stringent requirement for the reference input. Its application to a eight-channel 6-b time-interleaved analog-to-digital converter is demonstrated. |
URI: | http://dx.doi.org/10.1109/TCSI.2008.2008477 http://hdl.handle.net/11536/7142 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2008.2008477 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 56 |
Issue: | 6 |
起始頁: | 1102 |
結束頁: | 1114 |
顯示於類別: | 期刊論文 |