鍺與矽晶圓接合介面形態與電性研究

Abstract

鍺與矽晶圓應用在光電元件上近年來備受矚目，晶圓接合技術可將異質材料作整合，達到高品質的接合介面。材料歷經同軸應力與高溫退火，在試片的表面形成化學鍵結以增加接合強度。但是不同材料之間存在熱膨脹係數差異的問題，在降溫過程中產生的熱應力會導致試片破裂或是試片分離等情況。 本實驗選擇P型矽/鍺與N型矽/鍺作為直接接合技術研究的材料。首先在矽試片上製作網狀結構，以克服熱應力使得試片可以在高溫退火後成功接合，接著再以穿透式電子顯微鏡觀察介面微結構型態並作電流電壓特性量測。結果顯示存在介面的非晶質區域厚度會隨著退火溫度升高而變薄。而電性量測方面則觀察到崩潰電壓與起始電壓皆會隨著退火溫度的上升而下降，此現象與存在介面的非晶質厚度有關。電性量測結果與能帶對準圖比較，發現高溫退火下並不符合能帶對準圖的趨勢，推測是由於鍺原子與矽原子相互擴散造成陷阱輔助穿隧效應，使得載子可以穿越能障在介面間導通。

Silicon and Germanium integrated for applications in optical communication systems and interconnection have attracted much attention. The formation of a heterojunction between hybrid materials by wafer bonding technique has been generally successful. During high pressure and high temperature annealing process, wafers are bonded by producing covalent bonds at interface. However, the high temperature annealing produced cracks in both wafers caused by large difference in the thermal expansion coefficients of Ge and Si, resulting in low yield for device fabrication. In this study, direct wafer bonding technique was applied to combine p-type Ge/Si and n-type Ge/Si. First, mesa structures fabricated on silicon wafers were used to avoid thermal stress during high temperature annealing process. The interface microstructure was investigated by transmission electrical microscopy (TEM) and I-V characteristic was also measured. The thickness of amorphous decreased with the annealing temperature increasing. The result of the I-V measurement also showed that the breakdown and the turn-on voltage decreased with the annealing temperature increasing, because the thickness of amorphous at interface changed with temperature. Results of I-V measurements and energy band diagram found that high temperature annealing did not meet the trend of the energy band alignment diagram, presumably due to germanium atoms and silicon atoms diffused between interfaces and caused the trap-assisted tunneling effect, the carriers could cross the barrier at interface.