標題: 應用於行動照護之低功耗生醫訊號處理器設計
Low Power Biomedical Signal Processor Designs for Mobile Healthcare Applications
作者: 許書餘
Hsu, Shu-Yu
李鎮宜
Lee, Chen-Yi
電子工程學系 電子研究所
關鍵字: 生醫;行動照護;低功耗;心臟;心電圖;處理器;壓縮;特徵擷取;症狀偵測;感測器;biomedical;mobile healthcare;low power;cardiac;Electrocardiogram (ECG);processor;compression;feature extraction;syndrome detection;sensor
公開日期: 2012
摘要: 無線裝置與微型化技術的蓬勃發展,為行動健康照護應用帶來了新的可能性,藉由配戴在人體或是植入式的無線感測模組,人體的生理訊號將可被連續的紀錄,並傳送至後端服務平台以完成進一步的分析。為了延長感測模組的觀測時間,感測模組可加入生醫訊號處理器,藉以即時地萃取重要訊息以減少需要的儲存記憶體與傳輸資料。然而,考慮各式應用與更長的觀測時間,生醫訊號處理器的設計須具備彈性、具備準確分析的能力,並且僅消耗非常低的功率。 有鑑於此,本論文將著重於演算法、硬體架構、與電路的設計,以達到低功率生醫訊號處理的需求。並使用心臟訊號相關的心電圖、向量心電圖、與心音圖完成系統展示,藉由現有與自行建立之資料庫以驗證分析效能。首先,本論文提出適用於行動照護觀測系統的資料處理流程,適合用於設計具備彈性與低功耗的生醫訊號處理器,藉由異質處理架構並減少處理器開啟時間,同時達到較佳系統彈性與運算效率。 接著,本論文提出一多通道心臟訊號處理器以同時滿足低功率訊號觀測與高品質診斷需求。有鑑於大部分處理器功率消耗被記憶體所佔據,動態壓縮引擎有效地減少25-90%持續開啟的記憶體。基於壓縮的資料,心電圖與向量心電圖的特徵擷取準確率仍可達99%以上。此心臟訊號處理器製作於90奈米標準CMOS製程,藉由降低工作電壓、兩階段的工作週期控制、與壓縮的記憶體,此處理器操作於0.5/1.0V並於不同工作組態消耗22.6μW至46.5μW功率。另一方面,為了提升系統功能,處理器亦整合生醫電位感測電路與電容感測電路,並各消耗10.2μW與11.4μW功率。 在功率消耗之外,生醫訊號處理器最關鍵的挑戰即為訊號分析之準確率。因此,本論文亦提出一基於機器學習的心臟訊號感測單晶片,藉以得到較傳統DSP演算法更佳的分析準確率。使用機器學習的特徵擷取與分類技術,並以自行及公開之資料庫驗證,此晶片可達95.8%以上的心律不整偵測率與99%以上的心肌梗塞偵測率。此外,由行動環境中造成的動作干擾也將藉由資料管理技術作補償。此心臟訊號感測單晶片製作於90奈米標準CMOS製程,搭配低工作電壓、非同步架構、電源閘與其他低功耗設計技術,處理器在各式心臟訊號分析應用僅消耗7.0μW至32.8μW功率。與感測電路整合,此單晶片在0.5V與1.0V工作電壓下,消耗 48.6/105.2μW 功率以完成心律不整/心肌梗塞的即時偵測。 藉由所提出的關鍵技術,本論文提出之演算法在無線感測模組中完成準確的分析,因此降低訊號觀測所需的傳輸資料。並由於低功率的處理器設計,使得無線感測模組的觀測時間大幅延長,以做為適用於行動健康照護應用的解決方案。
The advances in wireless devices and miniaturized sensors fuel the possibilities of mobile healthcare applications, where the wireless sensor nodes (WSNs) are body-worn or implanted for continuous vital signal recording. To extend the WSN monitoring duration, on-sensor biomedical signal processors (BSPs) can be applied to timely extract the critical information for reduced storage and transmission data. Considering the supports to versatile applications with maximized monitoring time, the BSPs should be flexible and accurate with extremely low power operation. This dissertation focuses on the algorithms, architectures and circuits for low power biomedical signal processing. The cardiac signal of electrocardiogram (ECG), vector- cardiogram (VCG) and phonocardiogram (PCG) from open-source and in-house databases are applied for system performance evaluation. The processing flow is first proposed for the mobile healthcare monitoring systems, enabling the flexible and low power BSP architecture. The heterogeneous processing architecture with duty-cycling operation scheme possesses both the system flexibility and power efficient computations. A multi-channel cardiac signal processor (CSP) is then introduced for both low power monitoring and high quality diagnosis requirements. As the most processor power is dominated by memory, the adaptive compression engine reduces 25-90% always-on storage. Moreover, the detection rate of the critical ECG/VCG fiducial point extraction is still over 99% using the compressed data. The CSP is manufactured in 90 nm standard CMOS technology. Based on voltage scaling, two-stage duty-cycling and compressed storage, the CSP consumes 22.6μW to 46.5μW at 0.5/1.0V in different configurations. Besides, the 10.2μW biopotential and 11.4μW capacitive sensor interfaces further enhance the system functionality. A key BSP challenge is the analysis accuracy. Hence a machine learning (ML) based cardiac sensor SoC (CS-SoC) is proposed to further enhance the accuracy over traditional DSP algorithms. Applied with the ML based feature extraction and classification techniques to the in-house and open-source databases, the cardiac syndrome detection rate of the arrhythmia and myocardial infarction (MI) achieves 95.8% and 99%, respectively. In addition, the motion artifacts induced in mobile environments are corrected during data management. The CS-SoC is fabricated in a 90 nm standard CMOS technology. Applied with voltage scaling, asynchronous architecture, power gating and other low power techniques, the processor dissipates 7-32.8μW for versatile cardiac signal analysis. Integrated with sensor interfaces, the CS-SoC power is 48.6/105.2μW at 0.5-1.0V for real-time arrhythmia/MI detection. As a result, the BSP chips based on the proposed key techniques show accurate on-sensor analysis and reduce the transmission data for the cardiac signal monitoring. Besides, the low power BSPs extend the WSN monitoring duration and provide suitable solution for mobile healthcare applications.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611844
http://hdl.handle.net/11536/71834
Appears in Collections:Thesis