使用共振耦合技術的功率合併設計

Abstract

功率合併對CMOS功率放大器而言，是個可以有效增加輸出功率的一個方式。變壓器常用來當作功率合併器。通常變壓器的電磁耦合係數被希望是越高越好。在這篇論文中，兩個5 GHz的AB級功率放大器路徑以共振耦合技術結合。共振耦合網路在很窄的頻段中可以視為理想的變壓器，所以對我們的設計而言，電磁耦合係數較不敏感。 此項設計包含了一個驅動放大器，兩個功率放大器還有一個串連變壓器。放大器皆是用疊接的偽差動對。在功率放大級有加上一個由電阻串連電容的回授路徑來增加穩定度。此設計是使用TSMC 0.18-μm CMOS製程。飽和的輸出功率是25.01 dBm，最大功率附加效率是24.81 %。在3.3V的供應電壓下，DC功率是1.27W。晶片大小是1840×1180 μm^2。

Power combining is an effective way to increase total output power for CMOS power amplifiers. Transformers are often used for power combining. Usually, the magnetic coupling coefficient, k, of a transformer is desired as higher as possible. In this thesis, two power paths of 5 GHz class-AB power amplifiers are combined using resonator coupling technique. The resonant coupling network can be seen as an ideal transformer in a narrow band frequency, so the magnetic coupling coefficient is more insensitive to our design. The design includes a driver amplifier, two power amplifiers, and a series transformer. The amplifiers are all pseudo-differential pairs with cascode topology. A feedback path with a capacitor and a resistor in series is used in the power amplifier stage. It increases the stability. The design is implemented in TSMC 0.18-μm CMOS technology. The saturated output power is 25.01 dBm and the maximum PAE is 24.81%. The power consumption is 1.27 W from a 3.3V supply. The chip size is 1840 ×1180 μm^2.