電網同步之鎖相迴路控制器的設計與分析

Abstract

本論文主要探討電網上鎖相迴路中控制器的設計以及利用模擬比較電網發生故障時各種控制器響應的結果。因為同步參考框鎖相迴路無法處理三相電壓不平衡的故障，因此多重參考框鎖相迴路或雙通用積分器鎖相迴路等鎖相迴路被提出，這些鎖相迴路的控制器大多是利用比例積分回授控制來實現，這種控制器在反應速度和高頻抑制都有出色的表現，但因為零點的關係有最大超越量較大的問題。為改善此問題利用虛擬微分回授控制、自適性調整之比例積分控制和Q參數化等方式來設計控制器，並且分析這些控制方式的參數對線性化系統的暫態響應與高頻抑制能力的影響。在符合所需的規格要求下，利用最小的單位步階誤差絕對值積分和誤差平方積分兩種指標作為模擬時參數的選擇，在各種不同的電網故障條件時，如相位變化、雜訊干擾以及頻率變化，藉由誤差的指標、總諧波干擾以及穩態誤差比較各個控制器在實際系統中之優點及缺點。

The thesis investigates grid synchronization phase locked loop (PLL) controllers design and compares the simulation results when grid fault occurs. Because synchronous reference frame PLL has poor phase-tracking performance when the voltage is unbalanced, others like multiple reference frame PLL and dual second order generalized integrator PLL are presented to overcome this drawback. These advanced PLLs controller also use the proportional integral (PI) controller. In general PI controllers can be designed to have fast response and effective attenuation of high order harmonics. The existence of a zero usually results in large overshoot in step response. This work presents pseudo-derivative feedback control, adaptive PI control and Q parameterization for better dynamic response, and the parameters are designed using the linear model with the minimum integral absolute error and integral square error in unit step response. Simulation results of these controllers under grid faults conditions are used to compare their performances.