奈米尺度物理模擬器之發展

Abstract

根據黃氏定律，記憶體元件的微縮化正急速驅近於光刻印術的商轉極限。在此同時，對最低bit cost記憶體元件的強勁需求推動著產業界研發更先進的光刻印術。很快的，光刻印術的商轉極限將會抵達連續性假設的極限。

首先，我們對計算浮動區域的自電位時的尺寸效應做討論。傳統上，我們透過調整共軛電容比參數決定揮發性記憶體的浮動閘極自電位。但是當記憶體元件的尺寸突破10nm後，浮動區域的表面電子數量是沒辦法良好定義的。因此，我們必須要將共軛電容比參數從奈米尺度模擬中剔除。透過使用渡邊教授所提倡的kicking演算法，我們成功的展示在不使用共軛電容比下計算出浮動區域的自電位。接著，我們討論了這個演算法如何構築後Drift-Diffusion理論的基石。作為成果，我們發現了單電子敏度讓我們可以偵測到元件中單一電子的移動事件。這項成果對於開發邏輯元件與記憶體元件都會有極大的助益。

在這份論文裏面，我們扼要的討論了Kicking演算法以及如何套用到三維物理模擬的暫態分析上。我們模擬的成果清楚的顯示出了施加電壓與浮動區域自電位之間明確的線性關係，也因此讓我們可以定義出等效共軛電容比。在能夠定義等效共軛電容比之後，我們可以在不使用參數調整下輕鬆的得到浮動區域的自電位。作為副產品，這讓傳統的TCAD模擬能夠延續下去。除此之外，除了我們所模擬的浮動球以外，我們的物理模擬器還能模擬傳統的浮動閘極記憶體，分子元件以及與可靠度問題息息相關的dangling-bond。以這篇碩士論文為出發點，我們將會繼續我們的一般性元件模擬器的開發。

According to Hwang's law, the scaling of the memory devices is rapidly approaching to the commercial limit of the lithography. On the other hand, the strong demand of lowest bit cost has still pushed us to develop further advanced lithography. Sooner or later, the commercial limitation might be close to the limitation of the continuity assumption.

Firstly, we focus on the size effect for calculating the self-potential of the floating island. Conventionally, the capacitance coupling ratio ($C_r$) has been used as the fitting parameter to determine the self-potential of the floating gate (one example of floating islands) inside the non-volatile memory. When the memory devices goes beyond $10nm$ generations, the surface charge of the floating island shall become ill-defined. Therefore, we need to remove this fitting parameter from nano-scale simulation. By using the kicking algorithm proposed by Watanabe, we successfully demonstrate how to calculate the self-potential without the fitting parameter .Secondly, we discuss that this algorithm is valid to formulate the post Drift-Diffusion model. As a result, it is successfully found that the Single-Electron Sensitivity enable us to monitor the hopping of sole electron via silicon dot (one example of floating islands). The sample structure that is tested here is the simplest in smallest volume. Therefore, the achievement that is obtained here is commonly useful to future logic device scaling as well as future memory devices.

In this thesis, we briefly describe the kicking algorithm and how to apply this algorithm to the transient three-dimensional device simulation. The result that will be demonstrated here clearly shows the excellent linearity of the self-potential and the applied voltage, which enable us to define equivalent capacitance ratio (ECr). The self-potential of the floating island can be calculated once we obtain the ECr without the fitting parameter. As byproduct, this makes the usage of TCAD much easier. Besides the floating dot that we simulate in this thesis, the present simulation method is powerful to floating gate memories, molecule devices, and the reliability issues related to dangling-bonds. In the PhD dissertation to be continued from this Master thesis, we will continue the development of the General-Purpose Device Simulator.