标题: | 基于PEG演算法之低密度同位元检查回旋码设计与实作 Design and Implementation of PEG based LDPC-CCs |
作者: | 吴升展 Wu, Sheng-Jhan 李镇宜 Lee, Chen-Yi 电子工程学系 电子研究所 |
关键字: | 低密度同位元检查回旋码;low-density parity-check convolutional codes;progressive edge growth;LDPC-CC;PEG |
公开日期: | 2013 |
摘要: | 低密度同位元检查回旋码(LDPC-CC)于1999年首次提出,是低密度同位元检查码中的回旋码版本。由于这种回旋码结构,低密度同位元检查回旋码高度适用于资料串流的应用。利用结尾 (tailing)与打点(puncture) 的技巧,框架大小(frame size)以及码率(code-rate)的调整可很单纯的达成。 在这个论文中,一个创新的编码建置演算法首先被提出,这个演算法不仅考虑错误更正能力,也考虑了硬体实作方面。模拟结果显示由此演算法所建置之低密度同位元检查回旋码所得的错误更正能力比IEEE标准规格、目前流行的拆开式(unwrapping)演算法、或是最新提出的多项式(polynomial)演算法所建造之码在不同的码率下都有更佳的结果。第二,我们建立一个完全可调式不需重新合成、放置与绕线之双FPGA验证平台来加速验证从我们所提之演算法建出之低密度同位元检查回旋码。与电脑模拟比较可达加速1000倍以上效果。从平台模拟结果了解我们的演算法的确建构可实作的低密度同位元检查回旋码,而且在低错误率区域也有出色的表现。最后,实作一个致力于人体通道通讯(body area network)低密度同位元检查回旋码低功率晶片,其中这个晶片的低密度同位元检查回旋码是特定为了错误更正能力而设计。量测结果显示,能量效率是19.8pJ/bit/proc比现有之低密度同位元检查回旋码解码器与回旋码之维特比(Viterbi)解码器有更佳的结果,且量测于0.6v资料传输率100Mb/s实解码器功率仅9.9mW,符合人体通道通讯之系统链路预算。 总结,一个创新之低密度同位元检查回旋码建置演算法在本论文中提出,其后为验证这些低密度同位元检查回旋码之双FPGA平台,另外是一个符合人体通道通讯之系统链路预算之低耗低密度同位元检查回旋码晶片。所有的结果都证实我们的演算法、验证平台以及晶片设计提供低密度同位元检查回旋码突破的思维与应用在下世代通讯系统的机会。 LDPC convolutional code (LDPC-CC), first introduced in 1999, is the convolutional version of LDPC code. Due to the convolutional structure, LDPC-CC is highly suitable for data streaming applications. And the variable frame size and code-rate adjustment through tailing scheme and puncturing are easily carried out. In this thesis, a novel code construction algorithm is firstly proposed for LDPC-CC construction, in which not only the performance but also the implementation aspects are considered. The simulation results show the LDPC-CCs derived from proposed algorithm outperform the codes no matter adopted by IEEE standards, derived from state-of-the-art unwrapping construction method, or found by the newly presented the polynomial based algorithm under different code-rate. Secondly, a fully configurable dual-FPGA emulation platform is built to accelerate the performance analyses of the LDPC-CCs derived from proposed algorithm without re-synthesis, placement and routing for a specific code. The speed-up compared with PC based simulations is more than 1000x. And the emulation results collected from the platform gives additional proofs that proposed algorithm generates implementable LDPC-CCs and they have outstanding performance even at the low bit error rate region. Finally, a LDPC-CC low power chip dedicated to the body area network is implemented, in which the code is specifically designed for performance requirement. The measurement results show the energy efficiency 19.8pJ/bit/proc is better than state-of-the-art LDPC-CC and convolutional code Viterbi decoder chip designs. And the decoder power 9.9mW measured at supply voltage 0.6v and data rate 100Mb/s satisfies the body area network system link budget. In summary, a novel code construction algorithm is proposed followed by a dual-FPGA true emulation platform built to verify the derived LDPC-CCs. And a low power LDPC-CC chip satisfying both the performance of the body area network and the power budget is presented. All the results are shown to examine that our proposed algorithm, platform, and chip design provide novel approaches to LDPC-CCs for next generation applications. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070050183 http://hdl.handle.net/11536/73202 |
显示于类别: | Thesis |