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dc.contributor.authorKo, Hou-Jenen_US
dc.contributor.authorTsai, Chun-Jenen_US
dc.date.accessioned2014-12-08T15:09:35Z-
dc.date.available2014-12-08T15:09:35Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0920-4en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/7323-
dc.identifier.urihttp://dx.doi.org/10.1109/ISCAS.2007.378382en_US
dc.description.abstractJava applications for embedded systems are becoming popular today. CLDC/MIDP is the standard application platform for mobile phones while CDC/PBP is the emerging application platform for next generation digital TV set-top boxes. Although software-based Java Virtual Machines (VM) are prevalent, most of these VMs require a host processor running at much higher clock rate than 300MHz to reach reasonable performance. This is beyond the recommended specification of handsets and set-top boxes. In this paper, we have proposed a double-issue java processor for embedded systems. The design is not tied to any host processors and can be used as an efficient binary execution engine for a full Java Runtime Environment implementation. When synthesized on a Virtex IV FPGA (4VFX12FF66-10), the RTL model can reach over 100MHz and consumes less than 22% resources of the device.en_US
dc.language.isoen_USen_US
dc.titleA double-issue java processor design for embedded applicationsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ISCAS.2007.378382en_US
dc.identifier.journal2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11en_US
dc.citation.spage3502en_US
dc.citation.epage3505en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000251608404145-
Appears in Collections:Conferences Paper


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