在後擺放器階段對繞線優化器所作的調查

Abstract

由於科技和製成的演進，IC設計變得越來越複雜。線路間延遲的重要性已經遠遠超過邏輯閘間的延遲。因為內部連結的數量級遠遠超過先前的設計，在超大型積體電路設計裡的繞線階段遭遇很多考驗。因此在擺放階段考慮可繞性是非常重要的一件事。 在[18]的研究中，在全域擺放階段只針對全域繞線優化電路的可繞性，可能產生一個不好擺置結果在細部繞線階段很難繞線。所以Ropt也關注全域繞線和區域繞線的不一致。 最近[19]提出了一個後置擺放器Ropt減少一個擺置結果的壅擠程度。Ropt先基於細部可繞性模型建立一個全域繞線的實例，此實例會引導Ropt重新擺置元件，接著會合法化元件位置，最後利用細部擺放進一步減少線長和擁擠。 這份研究改進Ropt的執行速度和結果品質。在改進品質方面，這份研究提出同時移動多個元件並且同時考慮繞線的實際樣式。我們也提出發散式的方法去重置元件。針對執行時間，我們則提出了最優區域和虛擬點。

As the technology node advances, IC design has become more complicated. The shrinkage of design is rapid. The interconnect delay already dominates the circuit delay. The scaling of interconnection oversteps the original design that the routing stage in the VLSI design encounters several challenges. Therefore, considering routability issues in the placement is very important. Notably, the work in [18] indicates that optimizing the placement’s routability only for global routing may get a hard-to-route placement in the detailed routing stage, so this work also pays attention to the mismatch of global routing and detail routing. Recently, a post-placer Ropt has been proposed [19] to reduce both global and local routing congestion levels of a given placement. Ropt constructs global routing instances on a local-routability-aware routing models that guides Ropt to relocate cell. A legalization scheme is followed to preserve the global placement. Finally, local detail placement further minimizes the local congestion and wirelength. This work enhances Ropt and improves its runtime and result quality. For improving the quality, this work presents a method to move multiple cells simultaneously and consider the real routing topology of net to preserve accuracy congestion map. We also propose a divergency-based cell relocating method. For runtime, we employ optimal region and pseudo point to speed up.