使用分散式觸發機制之高藏匿性硬體木馬設計與實現

Abstract

本論文提出了一個使用分散式的觸發型硬體木馬並以高階加密標準電路為應用觀察和量測不同觸發個數的區別，本研究實作三種不同的硬體木馬設計來比較功耗，觀察三個電路之不同功耗損耗的變化，進而了解硬體木馬藏匿程度的關係，我們分別用兩個和四個分散觸發來和一個觸發且未經分散觸發的電路來做為比較藏匿程度的結果，兩個和四個分散觸發的藏匿程度分別獲得48.91%和18.63%的改善。

In this thesis, a hardware Trojan horse (HTH) with distributed triggers in the triple data encryption standard (TDES) circuit is presented. Three HTH designs with different distributed triggers are developed and compared. The power consumption is profiled and evaluated with three different numbers of distributed triggers to see the effect of HTH hidden coverage. The hidden coverage improvement results using two and four distributed triggers are 48.91% and 18.63% compared with non-distributed one trigger circuit.