標題: | 高度整合非對稱多處理核心工作排程之設計與分析 Design and Analysis of a Unified Asymmetric Multiprocessors Scheduler |
作者: | 王志鵬 Chih-Peng Wang 蔡淳仁 Chun-Jen Tsai 資訊科學與工程研究所 |
關鍵字: | 非對稱多處理器;多核心多媒體系統;系統晶片;嵌入式作業系統;Asymmetric multiprocessors;multi-core multimedia systems;system-on-chip;embedded OS |
公開日期: | 2004 |
摘要: | 現今大多數嵌入式多媒體平台使用非對稱多處理核心平台。一個非對稱多處理核心通常包含一個通用型微處理器以及一個或多個數位訊號處理器。針對這樣的系統,目前大多數的工作分配是採用在開發時的靜態分配。然而在新世代多媒體處理系統中的多變性,當運作時的系統狀態與開發時所假設的系統狀態有所差異時,整體系統效能可能會有所降低。本論文提出一個在非對稱多處理核心系統上的動態高度整合工作排程,藉由此工作排程可以獲得較佳的系統效能。新的程式寫作方法類似多執行緒的程式寫作。初步的結果顯示本架構非常適合複雜的嵌入式系統。 Most embedded multimedia devices today uses asymmetric multiprocessor (AMP) platforms. An AMP is usually composed of a General Purpose Processor (GPP) core and one or more Digital Signal Processor (DSP) cores. For such systems, a common practice is to perform static task partition during development time. However, due to the dynamic nature of new generations of multimedia embedded systems, the performance of the system maybe hindered greatly when the runtime system state is different from the assumed static state at development time. This thesis proposes a dynamic asymmetric multiprocessor scheduling framework that can reach better runtime system performance by using a single unified task scheduler. A new programming practice similar to multi-thread programming is also proposed in order to facilitate this approach. Initial results show that this framework is very suitable for complex embedded systems. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009217605 http://hdl.handle.net/11536/74101 |
Appears in Collections: | Thesis |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.