支援多核心架構之可配置性混合型系統網路架構

Abstract

在多核心系統中，為了要達到優良的效能表現，在系統上的網路架構設計是一個重要的研究主題。以往的網路架構設計多是以針對某一特定應用來設計，然而固定型態的系統網路架構不能保證在所有的應用程序上都能達到最佳的效能表現。本文提出一種新的硬體架構設計: 可配置性混合型系統網路架構。透過和已知特性的傳輸通訊量的共同運作，可配置性混合型系統網路架構在適當的配置情況下能減少25%至40% 消耗在系統網路架構上的等待時間

To achieve superior performance of parallel applications on a Multi-Processor System on Chip (MPSoC), an effective and efficient interconnect design has been a critical research topic in architecture design for System on Chip. The conventional design of interconnection targets on specific applications with fixed configurations. However, a fixed interconnect architecture cannot be efficiently applied on applications with different characteristics. To address this issue, this thesis proposes a novel architecture and implementation of Reconfigurable Hybrid Interconnect (RHI) for MPSoC. By cooperating with known traffic characteristics, the proposed RHI has demonstrated an average of 25% to 40% of latency reduction by applying proper configurations.