标题: | 多执行绪Java处理器设计 Design of the Multithreading Architecture for a Java Processor |
作者: | 吴宗汉 Wu, Tsung-Han 蔡淳仁 Tsai, Chun-Jen 资讯科学与工程研究所 |
关键字: | Java处理器;执行绪;同步处理;多核心;电路设计;Java processor;thread;synchronization;multi-core;monitor;circuit design |
公开日期: | 2013 |
摘要: | 多执行绪在Java平台内是不可或缺的功能,例如web-browser内需要管理不同子视窗的连线、或者档案下载软体可能使用多个执行绪同时载入同个档案内不同的data block。在本论文中我们将以Java Application IP (JAIP)为基础,提出一个Multicore multithreaded Java processor Architecture,藉由同时执行多个Java处理器并且每个Java处理用上启用temporal multithreading机制,达到每个处理器资源使用最佳化并且能容纳更多执行绪,为了在我们提出的设计之中解决thread的分配与同步问题,我们也提出新架构用以协同每个Java处理器运作并且处理程式执行的一致性。此架构在Xilinx ML-605 FPGA平台上验证。实验结果显示,我们提出的架构比单一Java处理器启用temporal multithreading的执行效能有显着的提升,并且将大幅缩减电路资源使用。 In this paper, we present the design of a four-core Java SoC with a centralized hardware thread manager and a coherent data cache controller across four processor cores. The Java processor core used in the SoC is based on the Java Application IP (JAIP) [1]. For thread synchronization, we propose a hardwired data coherence controller to coordinate the data access of all threads. The proposed architecture has been implemented and verified on the Xilinx ML605 FPGA platform. The experimental results show that the proposed architecture is very efficient. For multithreading applications, the speedup of a four-core system can be up to 3.69 times faster than a single-core system, tested using popular parallel benchmark programs. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070156117 http://hdl.handle.net/11536/74492 |
显示于类别: | Thesis |
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