低操作電壓奈米級靜態隨機記憶體電路設計

Abstract

物聯網與可穿戴式裝置熱潮帶來了對低功耗記憶體的更殷切需求，需求的程度甚至超越目前智慧型手機與平板裝置。在許多低功率解決方案中，降低操作電壓是比較直接且簡單處理的技巧。然而隨著深次微米製程技術的開發，元件越做越小的情況下，元件特性的變化差異也越來愈顯著，這個也嚴格限制了靜態隨機記憶體的電壓操作範圍。目前業界所提供可量產的靜態隨機記憶體，皆無法確保在較低電壓下可以進行穩定的操作。在這篇論文中，我們提出四項輔助電路設計來強化靜態隨機記憶體在低電壓操作的穩定性。此外，我們也提出新架構的靜態隨機記憶體作為低電壓操作的新解決方案。最後，針對傳統雙埠靜態記憶體，提出創新的操作模式，來確保低壓操作的穩定性。

The Internet of Things (IoT) and wearable devices bring a more strong demand for low-power memory, even beyond the current level of demands for smartphones and tablet devices. In many low-power solutions, to reduce the operating voltage is a relatively straightforward and simple processing technique. However, with the development of deep sub-micron process technology, the variations and mismatch problems of the high density and high performance devices become more and more significant and the optimization of the design parameters are under the major consideration. This also strictly limits the voltage operating range of static random access memory. With the industry production static random access memory, there is no promise to access the memory under a stable circumstance at a lower voltage operation so far. In this thesis, we propose four auxiliary circuits to strengthen the stability of static random access memory at lower operation voltage. In addition, we also propose new solutions for the low VMIN improvement with the new 8T structure static random access memory. Finally, a novel operation scheme to improve the VMIN value is provided for the conventional dual-port static random access memory applications.